Number Of Clock Pulses Research Articles

Bootstrap-based frequency estimation method

Abstract In this paper, the bootstrap method was used to estimate the frequency of a signal. Here, the periodic signal was transformed into a rectangular wave and the interval of time between two consecutive positive edges of this rectangular wave was estimated. First, in order to estimate this interval of time, a counter was used to count the number of clock pulses that have occurred during every interval of this type. In this case, the clock frequency was the sampling frequency. Next, this process was repeated several times and a vector of estimated values of the period of the signal was created. After that, this vector was considered as a random sample and it was used to create thousands of resamples with the same size as the above-mentioned random sample and that were created by sampling with replacement from the original random sample. Then, for each resample, the sample mean was calculated and the inverse of the mean of these sample means was used as an estimation of the frequency of the signal. Finally, a prototype of this statistic method to frequency estimation was built. The results of the experiment were satisfactory.

Clustered NOC, a suitable design for group communications in Network on Chip

In this paper, a Clustered NOC (C-NOC) is introduced to improve the performance of Hermes-NOC (H-NOC) in group communication. Each C-NOC switch has eight bi-directional ports connected to four neighbor switches and four local ports. With the same (IP) cores in both H-NOC and C-NOC networks, the ordinal size of C-NOC is 75% less than H-NOC. In corner-to-corner communication, C-NOC operates 29% faster than H-NOC. In random traffic mode, when the size of network is increased, then the average delay time of a packet in C-NOC is reached to this value in H-NOC. In group communication, a group of four IP cores is attached to a switch. The average delay time of a packet and number of clock pulses in C-NOC are 19.7% and 13.6% less than their values in H-NOC, respectively. This high performance of C-NOC is resulted from its internal switching. These comparisons in group communication show that C-NOC has superiority over H-NOC.

Design and Implementation of KASUMI Algorithm in ISMACryp Encryption for Video Content Protection in DVB-H Application

Three technologies can be used for content protection in DVB-H; IPSec, SRTP and ISMACryp. ISMA Encryption and Authentication is one of the three chosen technologies for service protection in DVB-H (Digital Video Broadcasting - Handheld), the TV system for portable handheld devices. This paper deals with modification in ISMACryp. The ISMACryp is encoded with MPEG-4 video and MPEG-4 AAC (advanced audio coding), while leaving all structural data as it is. Two modes of ISMACryp are available; the CTR mode (Counter type) and CBC mode (Cipher Block Chaining) mode. Both modes of ISMACryp is based on 128-bit AES algorithm. AES algorithms are more complex and require larger time with more clock cycles for execution. This paper is being first simulate and implement existing ISMACryp using 128-bit Rijndael algorithm and then modified it with KASUMI algorithm that will be provided lower number of clock pulses with lower execution time. The simulation is done in Matlab and implementation in TMS320C6713 DSP kit.

Switched-capacitor circuits with periodical nonuniform individual sampling

The operation of switched-capacitor (SC) circuits with periodical nonuniform individual sampling (PNIS) is introduced. The basic idea consists in a time averaged control of the effective rate of charge delivered by any given SC structure. In this way, the equivalent resistance of each SC branch in a circuit is individually controlled by programming the number of clock pulses in which it is active in a predetermined period of time. It is shown that this additional design degree of freedom provides a very wide programmability range in all response parameters. A second-order SC filter programmable by PNIS has been designed and fabricated in conventional CMOS technology. Experimental results are in good agreement with theoretical ones, and demonstrate the effectiveness and versatility of the proposed technique for low-frequency applications.

Non-scan design for testable data paths using thru operation

In this paper a non-scan design method for testability using thru operation is proposed for register transfer level data paths. First, the weak testability of data paths is defined, and the problem of making data paths weakly testable with small overhead is considered. It is shown that this problem is NP-complete and a heuristic algorithm for solving it is presented. Next a measure for the number of clock pulses that are necessary to control and observe registers is proposed, and its relationship to the test generation time is discussed. Finally the effectiveness of the method and the proposed measures are demonstrated with the results of experiments.

A novel frequency comparator: applications in frequency meters and in difference clocks for generator frequency error monitors

Conventional methods of frequency measurement count the number of cycles in a given time or the number of clock pulses during one or more periods of the unknown signal. This approach is prone to error from the uncertainties associated with the gating of two signals. A novel comparator is described that eliminates this error. The frequency of an unknown signal is compared cycle for cycle with a reference. The comparator has two outputs; one of these indicates which of the two signals is at a lower (or higher), frequency while the other output is a pulse train with a repetition rate equal to the difference of the two frequencies. Applications of the comparator in difference clocks and in frequency meters are presented.

Detection accuracy in zero-crossing-based spectrum analysis and image reconstruction

We examine how the accuracy in describing the exact location of a signal crossing affects the quality of the spectrum or the reconstructed two-dimensional image that is computed by a representation of sampled zero crossings. The position of a zero crossing within a Nyquist interval is described by the ratio between the number of clock pulses that have elapsed before the crossing occurred and the total number of clock pulses that could fit within the interval. The pulses scale the Nyquist interval, and the greater their total number, the more accurate the description of the crossing location. In a real zero-crossing detector the ability to increase the total number of square pulses contained within the Nyquist interval is limited by the finite response time of its circuit components [Opt. Lett. 18, 1468 (1993)].

Digital Frequency Multiplier for Spectrum Measurement of Periodic Signals

Frequency multipliers find applications in the Fourier and Walsh spectrum measurements of periodic signals. Earlier digital frequency multipliers use two counters: 1) An upcounter which is partitioned into a fractional counter of kbits in cascade with an integral counter. This determines the period of the input signal by the number of clock pulses that are accumulated in a period of the signal. 2) A downcounter which is next fed from the same clock, and which is periodically preset to the contents of the integral counter whenever the downcounter reaches zero. In this process an error is introduced in the output frequency because the fractional counter contents are ignored in the frequency multiplication phase. To minimize this error, a high clock frequency is required so that the fractional count is small compared with the integral count. The maximum output pulse frequency is limited by the speed of the counters used. A new method is described which also uses the contents of the fractional counter. The clock frequency is reduced substantially and the maximum output pulse frequency is limited by the settling time of a D/A converter: If the settling time is 200 ns, the maximum output frequency is ten times that of earlier methods.

Memory Efficiency

Memory Efficiency