Non-volatile Main Memory Systems Research Articles

NVGraph: Enforcing Crash Consistency of Evolving Network Analytics in NVMM Systems

Many complex networks can be modeled as evolving graphs. Existing in-memory graph data structures are designed for DRAM. Thus, they cannot effectively exploit the current and ongoing adoption of emerging non-volatile main memory (NVMM) for two reasons. (1) Ephemeral graph data structures are not crash-consistent for NVMM. (2) NVMM writes and reads and may incur higher latency than DRAM. In this article, we propose a novel persistent evolving graph data structure, named NVG RAPH , for both computing and in-memory storage of evolving graphs in NVMM. We devise NVG RAPH as a multi-version data structure, wherein a minimum of one version of its data is stored in NVMM to provide the desired durability at runtime for failure recovery, and another version is stored in both DRAM and NVMM to reduce the NVMM-induced memory latency. NVG RAPH is also a partitioned data structure. We dynamically transform the layout of NVG RAPH (e.g., changing the size of its partition in DRAM) exploiting network properties and data access patterns of workloads. For the evaluation of NVG RAPH , we implement four representative real-world graph applications: pagerank, BFS, influence maximization, and rumor source detection. The experimental results show that the performance of NVG RAPH is comparable to other in-memory data structure (e.g., CSR and LLAMA) while using 70 percent less DRAM. It scales well up to 10 billion edges and 201 snapshots and supports crash consistency. It offers up to the 21X speedup of execution time compared to the scale-up graph computation approaches (e.g., GraphChi and X-stream).

Adaptive Writeback-aware Cache Management Policy for Lifetime Extension of Non-volatile Memory

In this paper, we propose Adaptive Writeback-aware Cache management (AWC) to prolong the lifetime of non-volatile main memory systems by reducing the number of writebacks. The last-level cache in AWC is partitioned into Least Recently Used (LRU) segment and LRU using Dirty block Precedence (DP-LRU) segment. The DP-LRU segment evicts clean blocks first for giving reuse opportunity to dirty blocks. AWC can also determine the efficient size of DP-LRU segment for reducing the number of writebacks according to memory access patterns of programs. In the performance evaluation, we showed that AWC reduced the number of writebacks up to 29% and 46%, and saved the energy of a main memory system up to 23% and 49% in a single-core and multi-core, respectively. AWC also reduced the runtime by 1.5% and 3.2% on average compared to previous cache managements for nonvolatile main memory systems, in a single-core and a multi-core, respectively.

Using DRAM as Cache for Non-Volatile Main Memory Swapping

The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory (NVM), which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the price and capacity of NVM are problematic. Therefore, the authors provide a large memory space without performance degradation by combining NVM with other memory devices. In this study, they propose a design for non-volatile main memory systems that use DRAM as a swap space. This enables both high performance and energy efficient memory management through dynamic power management in NVM and DRAM.

Ultra simple way to encrypt non‐volatile main memory

AbstractBuilding non‐volatile main memory (NVMM) systems requires the memory data to be encrypted to remedy the potential security vulnerability caused by the non‐volatile property of NVMM. Existing solutions still have shortcomings as vulnerability of security, inadequate optimizing of performance, and other limitations hold back their deployment into real systems. This paper proposes an address‐based counter mode encrypted NVMM system. It constructs a stand‐alone memory‐side secure engine to make counter mode encryption and maintains the crucial encryption parameter of counter by adopting the address‐based strategy. Compared with existing techniques, it provides the distinct advantages of: (1) higher assurance of security through encrypting any data at any time; (2) better performance, as nearly all of the encryption/decryption latencies are removed; (3) good feasibility due to the lowest‐level protection, ultra simple structure with low implementation cost, as well as no need for further adjustments, and it can also be made available for a wide range of target platforms; (4) helpful to improve the lifetime of NVMM without side‐effects to wear‐leveling techniques. Performance evaluation shows the overall performance slowdown has an average value of 0.072%, which proves the proposed method is an effectual way to implement data protection for NVMM systems. Copyright © 2014 John Wiley & Sons, Ltd.