Analog-to-digital Converters Nonlinearity Research Articles

Partial Sum Quantization for Computing-In-Memory-Based Neural Network Accelerator

Computing-in-memory (CIM) has been successful as an ideal hardware platform to improve the performance and efficiency of convolutional neural networks (CNNs). However, owing to the limited size of a memory array, the input and weight matrices of a convolution operation have to be split into sub-matrices, involving partial sums. Generally, high-resolution analog-to-digital converters (ADCs) are used to obtain partial sums for maintaining the computing precision, but at the cost of high area and energy. Partial sum quantization (PSQ), which can be exploited to significantly reduce the ADC’s resolution, is still an open question in this field. This paper proposes a novel PSQ approach for CIM using post-training quantization based on a newly defined array-wise granularity. Meanwhile, as the non-linearity of ADCs’ transfer function has a severe impact on the accuracy, a gradient estimation method based on smooth approximation is proposed to solve such a problem. Experiments on various CNNs show that the required ADCs’ resolution can be reduced from 11-bit to even 3-bit with slight accuracy loss ( 1.63%), and the energy-efficiency is increased by up to 224%.

Compensation of Non-linear Distortion Effects in MIMO-OFDM Systems Using Constant Envelope OFDM for 5G Applications

Orthogonal frequency division multiplexing (OFDM) is a multicarrier transmission system that can achieve high data rate over wireless channels. At the same time, multiple input multiple output OFDM (MIMO-OFDM) in wireless communication systems has been exposed to offer significant improvement over wireless technology by providing transmit diversity. It has become a promising technique for high-performance 5G broadband wireless communications. However, the main problem associated with MIMO-OFDM is that its signal exhibits high peak-to-average power ratio (PAPR), which causes nonlinear distortion and consequently performance degradation. Besides, PAPR carries weaknesses such as an increase in power consumption of high power amplifier (HPA) and analog to digital converter (ADC). Thus, 5G base stations will push up power requirements because energy consumption grows with the number of transceiver elements. So, mobile operators must find the right compromise that, on the one hand, guarantees a certain level of performance to a data flow, and, on the other hand, the energy cost generated for the deployment of the network. For this, as part of the management of power consumption, we propose MIMO constant envelope OFDM (MIMO-CE-OFDM) technique. In this work, we used MIMO-CE-OFDM to mitigate the nonlinear effect of HPA and ADC. To perform practical simulations, we have used COST 2100 MIMO channel model. In this paper, a MIMO-CE-OFDM system has been presented and analyzed under COST 2100 channel model conditions. Simulation results are given to illustrate the performance of [Formula: see text] MIMO-CE-OFDM in the presence of both HPA and ADC nonlinearity. This work shows that the effect of nonlinearity is shown to be negligible on MIMO-CE-OFDM signal.

SVM-Based Channel Estimation and Data Detection for One-Bit Massive MIMO Systems

The use of low-resolution Analog-to-Digital Converters (ADCs) is a practical solution for reducing cost and power consumption for massive Multiple-Input-Multiple-Output (MIMO) systems. However, the severe nonlinearity of low-resolution ADCs causes significant distortions in the received signals and makes the channel estimation and data detection tasks much more challenging. In this paper, we show how \textit{Support Vector Machine} (\textit{SVM}), a well-known supervised-learning technique in machine learning, can be exploited to provide efficient and robust channel estimation and data detection in massive MIMO systems with one-bit ADCs. First, the problem of channel estimation for uncorrelated channels is formulated as a conventional SVM problem. The objective function of this SVM problem is then modified for estimating spatially correlated channels. Next, a two-stage detection algorithm is proposed where SVM is further exploited in the first stage. The performance of the proposed data detection method is very close to that of Maximum-Likelihood (ML) data detection when the channel is perfectly known. We also propose an SVM-based joint Channel Estimation and Data Detection (CE-DD) method, which makes use of both the to-be-decoded data vectors and the pilot data vectors to improve the estimation and detection performance. Finally, an extension of the proposed methods to OFDM systems with frequency-selective fading channels is presented. Simulation results show that the proposed methods are efficient and robust, and also outperform existing ones.

A low‐power, low‐data‐rate efficient ADC with hybrid exponential‐linear transfer curve for bio‐potential recording systems

SummaryA digital‐ramp hybrid exponential‐linear analog‐to‐digital converter (ADC) is presented in this paper, which is attractive, where a high dynamic range (DR) is required. It is especially applicable for sampling neural (bio‐potential) signals, as most of the neural signal data are concentrated on higher side of the amplitude range. By the exponential quantization function for low signal amplitudes, the background noise that disperses in lower amplitudes will be reduced. For higher signal amplitudes, the exponential function optionally switches to linear function at an adjustable voltage threshold, to reduce required number of bits for those high amplitudes, as well. As a result of this exponential‐linear hybrid operation, the total data rate and the power required for data transmission are decreased. A prototype 8‐bit counter‐based exponential ADC is designed and simulated in 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS). The 20‐KS/s ADC achieves a DR of 66 dB, occupies 0.036 mm2 area, and consumes 6.4‐μW power from a 1.8‐V supply. Integral nonlinearity (INL) and differential nonlinearity (DNL) that are redefined to be compatible with nonlinear ADCs are 3.2 and 0.88 least significant bits (LSBs), respectively.

An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method

A novel ultrafast and low-cost pipelined analog-to-digital converter (ADC) testing and calibration method is proposed. The ADC nonlinearities are modeled as segmented parameters with interstage gain errors. During the test phase, a pure sine wave is sent as input and the model parameters are estimated from the output data with the system identification method. Significantly, fewer samples are required when compared to traditional histogram testing. The modeled errors are then removed from the digital output codes during the calibration phase. Extensive simulations have been run to verify the correctness and robustness of the proposed method. With just 4000 samples, a 12-bit ADC can be accurately tested and calibrated to achieve less than 1 least significant bit (LSB) integral nonlinearity (INL). Measurement results show that the ADC effective number of bits (ENOB) is improved from 9.7to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by 20 dB after calibration. The chip is fabricated in 40-nm technology and consumes 10.71 mW at a sampling rate of 125 MS/s.

A Fully Configurable Non-Linear Mixed-Signal Interface for Multi-Sensor Analytics

This paper presents a highly configurable non-linear compression scheme and its implementation as a configurable, compressive successive approximation register analog-to-digital converter (ADC). The non-linear ADC takes advantage of the input signal amplitude statistics and application sensitivity to maximize the information content of the digitized signal. This allows for potential power savings in the ADC conversion and the digital post-processing that follows it. This paper is the first mixed-signal interface that is fully configurable in terms of its non-linear quantization approach, supporting a wide variety of quantization functions. A 90-nm CMOS proof-of-concept chip operating at 33 kS/s is presented. The versatility and broad applicability of this proposal are further demonstrated with various case studies.

A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link

A 0.88 mm2 65-nm analog-to-digital converter (ADC)-based serial link transceiver is designed with a maximum-likelihood sequence detector (MLSD) for robust equalization. The MLSD is optimized in a pipelined look-ahead architecture to reach 10 Gb/s at 5.8 pJ/b and 5 Gb/s at 3.9 pJ/b, making it practical for an energy-efficient ADC-based serial link. Compared with linear equalizer and decision feedback equalizer, the MLSD provides extra margin to accommodate timing offsets, ADC nonlinearities, and voltage noise, which is exploited by co-designing the analog front-end to reduce its power and area. We present a 2x-oversampled and 2-way interleaved 5 b stochastic flash ADC architecture. No front-end analog equalizer, buffer or sample, and hold amplifier are needed. Tested with a 45-cm FR-4 trace, the serial link transceiver achieves 5 Gb/s at a bit error rate below 10−11 with a 7% UI margin without any analog front-end equalization, consuming 54.5 mW in receiver and 16.2 mW in transmitter.

Building the analytical response in frequency domain of AC biased bolometers

Context: Bolometers are high sensitivity detector commonly used in Infrared astronomy. The HFI instrument of the Planck satellite makes extensive use of them, but after the satellite launch two electronic related problems revealed critical. First an unexpected excess response of detectors at low optical excitation frequency for {\nu} < 1 Hz, and secondly the Analog To digital Converter (ADC) component had been insufficiently characterized on-ground. These two problems require an exquisite knowledge of detector response. However bolometers have highly nonlinear characteristics, coming from their electrical and thermal coupling making them very difficult to modelize. Goal: We present a method to build the analytical transfer function in frequency domain which describe the voltage response of an Alternative Current (AC) biased bolometer to optical excitation, based on the standard bolometer model. This model is built using the setup of the Planck/HFI instrument and offers the major improvement of being based on a physical model rather than the currently in use had-hoc model based on Direct Current (DC) bolometer theory. Method: The analytical transfer function expression will be presented in matrix form. For this purpose, we build linearized versions of the bolometer electro thermal equilibrium. And a custom description of signals in frequency is used to solve the problem with linear algebra. The model performances is validated using time domain simulations. Results: The provided expression is suitable for calibration and data process- ing. It can also be used to provide constraints for fitting optical transfer function using real data from steady state electronic response and optical response. The accurate description of electronic response can also be used to improve the ADC nonlinearity correction for quickly varying optical signals.

ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

Effect and compensation of ADC nonlinearity on magnetic accommodation measurements

In this paper we analyze how static errors of Analog-to-Digital converters (ADCs) can influence the measurement of magnetic accommodation in soft ferrite core. In a first analysis, the discussion is carried out through a series of simulated ADC INLs applied to simulated signals and experimental data. Possible impacts of the integral nonlinearity (INL) on the reconstruction of the B−H trajectory are shown. In a second phase, a real ADC INL is considered to better quantify the impact of real ADC errors on the measurements. An easy to implement procedure based on physical symmetry property of the material is presented and adopted to reduce the INL effect on magnetic accommodation measurements. Finally, a comparison between the proposed approach and a mid-point linearization compensation technique of INL is reported showing the validity of the presented procedure.

Digital post-calibration of a 5-bit 1.25 GS/s flash ADC

We report a high-speed flash analog to digital converter (ADC) linearization technique employing the inverse Volterra model and digital post processing. First, a 1.25 GS/s 5-bit flash ADC is designed using a 0.18 μm CMOS, and the signal is quantized by a distributed track-and-hold circuit. Second, based on the Volterra series, a proposed digital post-calibration model is introduced. Then, the model is applied to estimate and compensate the nonlinearity of the high-speed flash ADC. Simulation results indicate that the distortion is reduced effectively. Specifically, the ADC achieves gains of 4.83 effective bits for a 117.1 MHz frequency input and 4.74 effective bits for a Nyquist input at 1.25 GS/s.

An Output Response Analyzer Circuit for ADC Built-in Self-Test

In this paper, a structure of the output response analyzer (ORA) circuit for analog-to-digital converters (ADCs) built-in self-test (BIST) is presented. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to estimate the degradation of signal-to-noise ratio (SNR) value. The appropriate approximations of the testing parameters reduce difficulties in designing the complete ORA circuit. In addition, the feature of reusable hardware in the calculation of sine-wave reference histograms and the computing capability of ADCs' parameters further improves the ORA design. This design is compact and easily to be adjusted by different setting. The developed ORA circuits are synthesized in a 0.18-μm technology to analyze the outputs of an 8-bit ADC to verify the designs.

A Proposal for Concurrent Estimation of Static and Dynamic Nonlinearity of ADC

Despite great advances in very large scale integrated-circuit design and manufacturing, performance of even the best available high-speed, high-resolution analog-to-digital converter (ADC) is known to deteriorate while acquiring fast-rising, high-frequency, and nonrepetitive waveforms. Wave-form digitizers (ADCs) used in high-voltage impulse recordings and measurements are invariably subjected to such waveforms. Errors resulting from a lowered ADC performance can be unacceptably high, especially when higher accuracies have to be achieved (e.g., when part of a reference measuring system). Static and dynamic nonlinearities (estimated independently) are vital indices for evaluating performance and suitability of ADCs to be used in such environments. Typically, the estimation of static nonlinearity involves 10-12 h of time or more (for a 12-b ADC) and the acquisition of millions of samples at high input frequencies for dynamic characterization. ADCs with even higher resolution and faster sampling speeds will soon become available. So, there is a need to reduce testing time for evaluating these parameters. This paper proposes a novel and time-efficient method for the simultaneous estimation of static and dynamic nonlinearity from a single test. This is achieved by conceiving a test signal, comprised of a high-frequency sinusoid (which addresses dynamic assessment) modulated by a low-frequency ramp (relevant to the static part). Details of implementation and results on two digitizers are presented and compared with nonlinearities determined by the existing standardized approaches. Good agreement in results and time savings achievable indicates its suitability.

Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach

This work presents a new method to estimate the nonlinearity characteristics of analog-to-digital converters (ADCs). The method is based on a nonnecessarily polynomial continuous and differentiable mathematical model of the converter transfer function, and on the spectral processing of the converter output under a sinusoidal input excitation. The simulation and experiments performed on different ADC examples prove the feasibility of the proposed method, even when the ADC nonlinearity pattern has very strong discontinuities. When compared with the traditional code histogram method, it also shows its low cost and efficiency since a significant lower number of output samples can be used still giving very realistic INL signature values.

A Histogram-Based Testing Method for Estimating A/D Converter Performance

A sine-wave histogram-testing structure for analog-to-digital converters (ADCs) is proposed. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to the estimation of the degraded signal-to-noise ratio (SNR) value. Therefore, the relationships among these parameters are analyzed, and a single sine-wave histogram test can be performed to evaluate the ADC. With the appropriate approximations in the reference sine-wave histograms and the estimations of the ADC parameters, the realization of an ADC output analyzer circuit could be a simple task. An ADC output analyzer circuit is therefore developed and synthesized using a 0.18-mum technique to analyze the outputs of an 8-bit ADC and estimate its performances using the proposed method.

Histogram Tests for Wideband Applications

Characterization and testing of analog-to-digital converters (ADCs) are important for many reasons. A histogram test is a common method to characterize the linearity features of an ADC. Two commonly used stimulus signals are sine waves and Gaussian noise. This paper presents a metrological comparison between Gaussian and sine-wave histogram tests for wideband applications, that is, we evaluate the performance of the characterization of the ADC and the usability of postcorrection. A postcorrection procedure involves the characterization of the ADC nonlinearity and then the use of this information by processing the ADC output samples to remove the distortion. The results show that the Gaussian histogram test gives reasonable accuracy in measuring nonlinearities. However, it does not result in a suitable model for postcorrection in wideband applications. A single-tone sine-wave histogram will be a better basis for postcorrection. The best result can be obtained if the lookup table is trained with several single-tone sine waves in the frequency band.

Influence of ADC Nonlinearity on the Performance of an OFDM Receiver

This paper discusses the influence of the nonlinearity of analog-to-digital converters (ADCs) on the performance of orthogonal frequency division multiplexing (OFDM) receivers. We evaluate signal constellations and bit error rate performances while considering quantization errors and clippings. The optimum range for an ADC input amplitude is found as a result of the trade-off between quantization error and the effects of clipping. In addition, it is shown that the peak-to-average power ratio (PAPR) of the signal is not a good measure of the bit error rate (BER) performance, since the largest peaks occur only with very low probabilities. The relationship between the location of a subcarrier and its performance is studied. As a result, it is shown that the influence of the quantization error is identical for all subcarriers, while the effects of clipping depend on the subcarrier frequency. When clipping occurs, the BER performance of a subcarrier near the center frequency is worse than that near the edges.

A Complementary Metal–Oxide–Semiconductor Image Sensor with Analog Gamma Correction Using a Nonlinear Single-Slope Analog-to-Digital Converter

An image sensor has limited dynamic range while the human eye has a logarithmic response over a wide range of light intensity. Although the sensor gain can be set high to identify details in darker areas on an image, this high gain results in saturation in brighter areas. Therefore, gamma correction is essential to match the human eye response. However, the digital gamma correction degrades image quality, especially for darker areas on the image, due to the limited resolution and dynamic range of the analog-to-digital converter (ADC). In this paper, we propose a complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) with a compact nonlinear ADC which performs analog gamma corrections that use the full dynamic range. A CIS with the proposed nonlinear ADC was fabricated with a 0.35-µm CMOS process. The test results show that the analog gamma correction provides a 2.2 dB peak-signal-to-noise-ratio (PSNR) improved image quality, which is better than conventional digital gamma corrections.

Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals With Stimulus Error Identification and Removal

Linearity testing of analog-to-digital converters (ADCs) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. This paper introduces the stimulus error identification and removal (SEIR) method for accurately testing ADC linearity using signal generators that may be significantly less linear than the device under test. In the SEIR approach, two imprecise nonlinear but functionally related excitations are applied to the ADC input to obtain two sets of ADC output data. The SEIR algorithm then uses the redundant information from the two sets of data to accurately identify the nonlinearity errors in the stimuli. The algorithm then removes the stimulus error from the ADC output data, allowing the ADC nonlinearity to be accurately measured. For a high resolution ADC, the total computation time of the SEIR algorithm is significantly less than the data acquisition time and therefore does not contribute to testing time. The new approach was experimentally validated on production test hardware with a commercial 16-bit successive approximation ADC. Integral nonlinearity test results that are well within the device specification of /spl plusmn/2 least significant bits were obtained by using 7-bit linear input signals. This approach provides an enabling technology for cost-effective full-code testing of high precision ADCs in production test and for potential cost-effective chip-level implementation of a built-in self-test capability.

Linear Model-Based Testing of ADC Nonlinearities

In this brief, we demonstrate the procedures of linear model-based testing for the example of a 12-b Nyquist-rate analog-to-digital converter (ADC). In a production test environment, we apply this technique to two wafer lots of devices, and we establish that the model is robust with respect to its ability to reduce the uncertainty of the test outcome. Reducing this uncertainty is particularly beneficial for higher resolution devices, for which measurement noise increasingly corrupts the measured "signal" that is the nonlinearity of the device under test.