Compensation Of Non-idealities Research Articles

ISFET Pixel Array With Selectable Sensitivity and Bulk-Based Offset-Drift Nullification Capability for Reduction of Non-Ideality Effects

This article presents a monolithic, cost-effective, label free, low power, robust <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times2$ </tex-math></inline-formula> fully differential ion-sensitive field-effect transistor (ISFET) pixel array aimed at pH sensing. Each pixel is based on a differential readout architecture which eliminates need for additional non-ideality compensation circuitry. Additionally, the design offers the capability to correct for residual drift and trapped charge offset through substrate-based voltage adjustment during calibration. The design also provides a unique ability for selecting pH sensitivity according to the desired mode of operation which has not been demonstrated previously. We present experimental results obtained from the pixel array fabricated in an unmodified AMS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.35~\mu \text{m}$ </tex-math></inline-formula> CMOS process using a 3.3 V power supply. Each pixel demonstrates a differential sensitivity of 61 mV/pH when operated in high sensitivity mode and 25 mV/pH when operated in high non-ideality rejection mode over the entire pH range, with the ability to remove the already small drift of 0.3 mV/min and any offset mismatch by adjusting the substrate voltage.

Analysis and Compensation of Nonidealities in Frequency Multiplier-Based High-Frequency Vector Signal Generators

This paper expounds on the application of frequency multipliers for the frequency upconversion of amplitude- and vector-modulated signals to high frequencies. First, a complex baseband equivalent Volterra series behavioral model is derived for representing the envelope transformation of frequency multipliers. Based on this model, a low-complexity baseband digital predistortion (DPD) scheme is developed to mitigate unwanted distortions exhibited by the frequency multipliers. The proposed DPD scheme consists of three modules: 1) a polynomial predistorter (PD) is first employed to mitigate the memoryless (ML) distortions associated with the frequency conversion; 2) a $D$ th order root module is included to correct for the phase modulation (PM)–PM distortions exhibited by the frequency multiplier with a frequency multiplication factor of $D$ ; and 3) a pruned Volterra-based PD is added to correct for residual distortions attributed to the output stage. As a proof of concept using a low-complexity experimental setup, the proposed DPD scheme is used to linearize several frequency multipliers, namely, a frequency doubler with an output at 12.5 GHz, a frequency quadrupler to produce an output at 25 GHz, and a frequency tripler with an output at 63 GHz. The proposed DPD scheme showed excellent capacity to linearize these frequency multipliers when driven by orthogonal frequency division multiplexing signals with modulation bandwidths up to 400 MHz with less than 56 coefficients.

A Scalable ISFET Sensing and Memory Array With Sensor Auto-Calibration for On-Chip Real-Time DNA Detection.

This paper presents a novel CMOS-based system-on-chip with a 78 56 ion-sensitive field-effect transistor array using in-pixel quantization and compensation of sensor nonidealities. The pixel integrates sensing circuitry and memory cells to encode the ion concentration in time and store a calibration value per pixel. Temperature sensing pixels spread throughout the array allow temperature monitoring during the reaction. We describe the integration of the array as part of a lab-on-chip cartridge that plugs into a motherboard for power management, biasing, data acquisition, and temperature regulation. This forms a robust ion detection platform, which is demonstrated as a pH sensing system. We show that our calibration is able to perform readout with a linear spread of 0.3% and that the system exhibits a high pH sensitivity of 3.2 /pH. The complete system is shown to perform on-chip real-time DNA amplification and detection of lambda phage DNA by loop-mediated isothermal amplification.

Non-idealities Compensation in Full-Digital Receivers with Application to Ultra-Wide Band

Nowadays many transceivers adhere to full-digital design principles, with the basic operations performed in the analog domain (filtering, down-conversion) and the whole remaining processing postponed to the digital domain (including matched filtering and synchronization). Though the operations in the analog front-end are ideally reversible, hence no signal degradation should occur before the analog-to-digital conversion (thus preserving the information integrity), however the intrinsic non-idealities in the circuitry may introduce a certain level of distortion. In this paper we provide a simple and flexible approach for the compensation of these effects. We derive useful formulas for obtaining a digital compensation filter by means of a direct transformation of the analog system coefficients. This allows to easily perform the compensation in the digital domain via fast Fourier transform. To illustrate the procedure, the case-study of a ultra-wide band receiver is addressed. Numerical results show that an improvement of more than 1 dB can be obtained at bit-error rate of interest for the applications. Sample code is also provided for an easy implementation.

Smart Flow Sensor With On-Chip CMOS Interface Performing Offset and Pressure Effect Compensation

A single-chip smart flow sensor based on a thermal principle is presented. The device is fabricated through a commercial complementary metal-oxide-semiconductor (CMOS) process combined with a postprocessing procedure. A configurable electronic interface performing signal reading and nonideality compensation is integrated with the sensing structures on the same chip. The interface implements recently proposed approaches to offset and pressure effect compensation. Detailed experimental results are presented demonstrating correct operation of the proposed microsystem.

Enhanced monolithically integrated coherent 120° downconverter with high fabrication yield

Conventional monolithically integrated 90° downconverter suffers from hardware-induced non-linear constellation distortion, which gets worse far away from the central wavelength or when fabrication errors are taken into account. To overcome these problems, a 120° monolithically integrated downconverter with full compensation of hardware non-idealities has been proposed. It is numerically demonstrated that, in a realistic scenario exposed to the combined effects of fabrication tolerances and limited ADC resolution, this approach exhibits a significantly better signal dynamic range and a remarkable improvement of fabrication yield.

Repetitive-Control-Based Self-Commissioning Procedure for Inverter Nonidealities Compensation

High-performance sensorless ac drives require the exact knowledge of the motor phase voltages in the whole speed range. The use of voltage sensors may be eschewed if the reference voltage signals, generated by the control algorithm, can be used instead. To this aim, an accurate compensation of most of inverter nonidealities is essential. This paper presents a novel self-commissioning procedure for the cancellation of inverter nonidealities, based on repetitive control. The main advantage is that the compensation generated by the procedure automatically includes the insulated-gate bipolar transistor parasitic effects during current zero-crossing, whose exact knowledge is one of the major problems in most of the standard dead-time cancellation techniques. Despite its elaborated theoretical background, the method requires few computational resources, and it is easy to implement. Mathematical developments, design hints, and an extensive batch of successful experimental tests are included in this paper.

Analysis and compensation of transistor non-idealities in log-domain wave active filters

A very important issue concerning the implementation of log-domain filters in integrated form is the effect of BJT transistor non-idealities. This paper is dealing with the above practical problem in the design of log-domain wave filters. For this purpose, a detailed analysis of the effects of the non-idealities on the frequency behavior of log-domain wave active filters is performed. In addition, a systematic method for compensating the caused imperfections is introduced. The validity of the proposed compensation scheme has been verified through simulation results.

On the use of the Discrete-Time Convolution Model for the compensation of non-idealities within digital acquisition channels

In this paper techniques for the compensation of the overall non-idealities affecting the operation of digital data acquisition channels are proposed, which are based on the exploitation of a non-linear dynamic model of these measurement sub-systems. It is shown how the non-linear dynamic equations of the model, which inherently describe both the static and the dynamic non-linearities associated with the behaviour of the channel, can be numerically inverted, and more accurate information on the properties of the system input signal achieved, starting from the corrupted sample records available at channel output. The procedure is based on the identification of a non-linear problem on the basis of the Harmonic-Balance approach, which can be solved by means of different recursive algorithms according to the application-dependent best trade-off between numerical convergence robustness and computational cost.

Design of continuous-time sigma-delta modulators with arbitrary feedback waveform

This paper considers the discretization of continuous-time sigma-delta modulators without any constraint on the shape or duration of the feedback signal. A motivation for taking the shape of the feedback signal into account is the system-level compensation of nonidealities encountered in a practical design. Two different discretization approaches based on state-variables and the modified z transform are presented. Explicit formulas for an exact mapping between continuous-time and discrete-time modulators are derived. Subsequently, design of multistage continuous-time modulators using arbitrary feedback waveforms is discussed.

Two-path structure for high performance sigma-delta modulators

A new parallel time-interleaved architecture for a two-path second-order switched-capacitor (SC) sigma-delta modulator is presented. This structure allows doubling of the oversampling sampling ratio (OSR) and, in addition, leaves an idle clock phase available for compensation of nonidealities. Simulations show that the presented architecture has a low sensitivity to path mismatch.