Non-silicon Substrates Research Articles

Inductively coupled plasma etching of bulk tungsten for MEMS applications

As a promising material for bulk micromachining for MEMS applications, tungsten can be used as microneedles for medicine injection and tools for micro-inject molding, ultrasonic machining, and electrical discharge machining. However, it is difficult to fabricate microstructures with high aspect ratios and small feature sizes due to the excellent material of tungsten properties, such as chemical stability, high hardness, and high melting point. Here, an inductively coupled plasma (ICP) deep etching process is developed for bulk tungsten, and its process parameters are studied. After optimizing the process parameters, three recipes were developed for different MEMS applications. A patterned tungsten structure with a depth of more than 300 µm was etched by tungsten (W) ICP deep etching (WIDE) at an etch rate of 2.73 µm/min and etch selectivity of 35. The WIDE process produced a tungsten microstructure with a high aspect ratio (> 20), a small feature size (< 3 µm), and a surface roughness of Ra 30 nm. To demonstrate the potential application prospect of deep etching bulk of tungsten, tungsten microneedles with a positive sidewall angle and several non-silicon substrates for MEMS applications were achieved based on the WIDE process. • Bulk tungsten ICP deep etching process development based SF 6 +O 2 +C 4 F 8 . • Effect of process parameters on ER, ES, DUR, roughness, sidewall angle. • μ-structures with > 300 µm deep, > 20 AR, and Ra 30 nm roughness. • Die steel, glass, and polymer μ-structures machined by etched tungsten. • Metal-based and non-silicon-based MEMS application prospect.

Silicon‐Compatible Photodetectors: Trends to Monolithically Integrate Photosensors with Chip Technology

AbstractEncouraged by the increasing requirements of intelligent equipment, silicon integrated circuit–compatible photodetectors that support single‐chip photonic–electronic systems have gained considerable progresses. Advanced materials have resulted in enhanced device performance based on traditional photovoltaic effect and photoconductive effect, and novel device designs have catalyzed new working mechanisms combing rapid photoresponse and high responsivity gain. Surprising applications are developed using monolithic photonic–electronic platforms, and the developing integration strategies keep pace with the developing complementary metal‐oxide‐semiconductor techniques as well as nonsilicon substrates. Here, the recent developments in silicon‐compatible photodetectors, both in device advances and their integration routes, are reviewed. Meanwhile, the progresses, challenges, and possible future directions in this field are discussed and concluded.

Remote epitaxy through graphene enables two-dimensional material-based layer transfer.

Epitaxy-the growth of a crystalline material on a substrate-is crucial for the semiconductor industry, but is often limited by the need for lattice matching between the two material systems. This strict requirement is relaxed for van der Waals epitaxy, in which epitaxy on layered or two-dimensional (2D) materials is mediated by weak van der Waals interactions, and which also allows facile layer release from 2D surfaces. It has been thought that 2D materials are the only seed layers for van der Waals epitaxy. However, the substrates below 2D materials may still interact with the layers grown during epitaxy (epilayers), as in the case of the so-called wetting transparency documented for graphene. Here we show that the weak van der Waals potential of graphene cannot completely screen the stronger potential field of many substrates, which enables epitaxial growth to occur despite its presence. We use density functional theory calculations to establish that adatoms will experience remote epitaxial registry with a substrate through a substrate-epilayer gap of up to nine ångströms; this gap can accommodate a monolayer of graphene. We confirm the predictions with homoepitaxial growth of GaAs(001) on GaAs(001) substrates through monolayer graphene, and show that the approach is also applicable to InP and GaP. The grown single-crystalline films are rapidly released from the graphene-coated substrate and perform as well as conventionally prepared films when incorporated in light-emitting devices. This technique enables any type of semiconductor film to be copied from underlying substrates through 2D materials, and then the resultant epilayer to be rapidly released and transferred to a substrate of interest. This process is particularly attractive in the context of non-silicon electronics and photonics, where the ability to re-use the graphene-coated substrates allows savings on the high cost of non-silicon substrates.

Film forming properties of silicon nanoparticles on SixNy coated substrates during excimer laser annealing

In this article we investigate the film forming properties of excimer laser annealed silicon nanoparticles on non-silicon substrates. In contrast to their film forming properties on oxide free silicon substrates, the nanoparticle thin film tends to dewet and form a porous µ-structure on the silicon nitrite covered glass model substrates considered for our investigation. This is quantified using a SEM study in conjunction with image processing software, in order to evaluate the µ-structure size and inter µ-structure distance in dependence of the laser energy density. To generalize our results, the film forming process is described using a COMSOL Multiphysics ® fluid dynamics model, which solves the Navier Stokes equation for incompressible Newtonian fluids. To account for the porous nanoparticle thin film structure in the simulation, an effective medium approach is used by applying a conservative level set one phase method to our mesh. This effort allows us to predict the Si melt film formation ranging from a porous Si µ-structure to a compact 100% density Si thin film in dependence of the substrate / thin film interaction, as well as the laser energy used for the nanoparticle processing.

Poly-crystalline thin-film by aluminum induced crystallization on aluminum nitride substrate

Thin-film polycrystalline silicon (pc-Si) on foreign (non-silicon) substrates has been researched by various research groups for the production of photovoltaic cells. High quality pc-Si deposition on foreign substrates with superior optical properties is considered to be the main hurdle in cell fabrication. Metal induced crystallization (MIC) is one of the renowned techniques used to produce this quality of material. In the current study, an aluminum induced crystallization (AIC) method was adopted to produce pc-Si thin-film on aluminum nitride (AlN) substrate by a seed layer approach. Aluminum and a-Si layer were deposited using an e-beam evaporator. Various annealing conditions were used in order to investigate the AIC grown pc-Si seed layers for process optimization. The effect of thermal annealing on grain size, defects preferentially crystallographic orientation of the grains were analyzed. Surface morphology was studied using an optical microscope. Poly-silicon film with a crystallinity fraction between 95-100% and an FWHM between 5-6 cm−1 is achievable at low temperatures and for short time intervals. A grain size of about 10 micron can be obtained at a low deposition rate on an AIN substrate. Similarly, Focused ion beam (FIB) also showed that at 425 °C sample B and at 400 °C sample A were fully crystallized. The crystalline quality of pc-Si was evaluated using μ-Raman spectroscopy as a function of annealed conditions and Grazing incidence X-ray diffraction (GIXRD) was used to determine the phase direction of the pc-Si layer. The current study implicates that a poly-silicon layer with good crystallographic orientation and crystallinity fraction is achievable on AIN substrate at low temperatures and short time frames.

Investigation of polycrystalline ferroelectric tunnel junction

Ferroelectric tunnel junction (FTJ) is a breakthrough for addressing the nondestructive read in the ferroelectric random access memories. However, FTJs with nearly ideal characteristics have only been demonstrated on perovskite heterostructures that are deposited on closely lattice-matched and non-silicon substrates, or silicon substrates with epitaxial multilayer. In order to promote the application of FTJs, we develop a polycrystalline FTJ with ultrathin bottom electrode, in which the resistance variations exceed two orders of magnitude. And we achieve two stable logic states written and read easily using voltage pulses. Especially the device integrates with the silicon technology in modern microelectronics. Our results suggest new opportunities for ferroelectrics as nonvolatile resistive switching memory.

Instantaneous room temperature bonding of a wide range of non-silicon substrates with poly(dimethylsiloxane) (PDMS) elastomer mediated by a mercaptosilane.

This paper introduces an instantaneous and robust strategy for bonding a variety of non-silicon substrates such as thermoplastics, metals, an alloy, and ceramics to poly(dimethylsiloxane) (PDMS) irreversibly, mediated by one-step chemical modification using a mercaptosilane at room temperature followed by corona treatment to realize heterogeneous assembly also at room temperature. The mercapto functional group is one of the strongest nucleophiles, and it can instantaneously react with electrophiles of substrates, resulting in an alkoxysilane-terminated substrate at room temperature. In this way, prior oxidation of the substrate is dispensed with, and the alkoxysilane-terminated substrate can be readily oxidized and irreversibly bonded with oxidized PDMS at room temperature. A commercially available Tesla coil was used for surface oxidation, replacing a bulky and expensive plasma generator. Surface characterization was conducted by water contact angle measurement and X-ray photoelectron spectroscopy (XPS) analysis. A total of fifteen non-silicon substrates including polycarbonate (PC), two types of poly(vinylchloride) (PVC), poly(methylmethacrylate) (PMMA), polystyrene (PS), polyimide (PI), two types of poly(ethylene terephthalate) (PET), polypropylene (PP), iron (Fe), aluminum (Al), copper (Cu), brass, alumina (Al2O3), and zirconia (ZrO2) were bonded successfully with PDMS using this method, and the bond strengths of PDMS-PMMA, PDMS-PC, PDMS-PVC, PDMS-PET, PDMS-Al, and PDMS-Cu assemblies were measured to be approximately 335.9, 511.4, 467.3, 476.4, 282.2, and 236.7 kPa, respectively. The overall processes including surface modification followed by surface oxidation using corona treatment for bonding were realized within 12 to 17 min for most of the substrates tested except for ceramics which required 1 h for the bonding. In addition, large area (10 × 10 cm(2)) bonding was also successfully realized, ensuring the high reliability and stability of the introduced method.

Non-silicon substrate bonding mediated by poly(dimethylsiloxane) interfacial coating

In this paper, we introduce a simple and robust strategy for bonding poly(dimethylsiloxane) (PDMS) with various thermoplastic substrates to fabricate a thermoplastic-based closed microfluidic device and examine the feasibility of using the proposed method for realizing plastic–plastic bonding. The proposed bonding strategy was realized by first coating amine functionality on an oxidized thermoplastic surface. Next, the amine-functionalized surface was reacted with a monolayer of low-molecular-weight PDMS, terminated with epoxy functionality, by forming a robust amine-epoxy bond. Both the PDMS-coated thermoplastic and PDMS were then oxidized and permanently assembled at 25°C under a pressure of 0.1MPa for 15min, resulting in PDMS-like surfaces on all four inner walls of the microchannel. Surface characterizations were conducted, including water contact angle measurement, X-ray photoelectron spectroscopy (XPS), and fluorescence measurement, to confirm the successful coating of the thin PDMS layer on the plastic surface, and the bond strength was analyzed by conducting a peel test, burst test, and leakage test. Using the proposed method, we could successfully bond various thermoplastics such as poly(methylmethacrylate) (PMMA), polycarbonate (PC), polystyrene (PS), and poly(ethylene terephthalate) (PET) with PDMS without the collapse or deformation of the microchannel, and the proposed method was successfully extended to the bonding of two thermoplastics, PMMA, and PC.

Electrical behavior of atomic layer deposited high quality SiO2 gate dielectric

Comprehensive and systematic electrical studies were performed on fabrication of high quality SiO2 thin films MOS capacitor using the robust, novel, and simple atomic layer deposition (ALD) technique using highly reactive ozone and tris (dimethylamino) silane (TDMAS) precursors. Ideal capacitance–voltage curve exhibits a very small frequency dispersion and hysteresis behavior of the SiO2 MOS capacitor grown at 1 s TDMAS pulse, suggesting excellent interfacial quality and purity of the film as probed using x-ray photoelectron studies. The flat-band voltage of the device shifted from negative toward positive voltage axis with increase of TDMAS pulses from 0.2 to 2 s. Based on an equivalent oxide thickness point of view, all SiO2 films have gate leakage current density of (5.18 × 10−8 A/cm2) as well as high dielectric break down fields of more than (∼10 MV/cm), which is better and comparable to that of thermally grown SiO2 at temperatures above 800 °C. These appealing electrical properties of ALD grown SiO2 thin films enable its potential applications such as high-quality gate insulators for thin film MOS transistors, as well as insulators for sensor and nanostructures on nonsilicon substrates.

Aluminum-induced crystallization for thin-film polycrystalline silicon solar cells: Achievements and perspective

Thin-film polycrystalline silicon (pc-Si) solar cell technology tries to combine the cost benefit of thin-film technology and the quality potential of crystalline Si technology. For this type of solar cells the challenge is to fabricate high quality coarse-grained (grain size of 1–100 µm) layers on non-silicon substrates in combination with superb light management. One possible material fabrication approach is metal induced crystallization (MIC). Many metals lower the crystallization temperature of a-Si but for photovoltaic (PV) solar cell applications aluminum seems to be the most interesting. Approximately a decade after the suggestion of Nast et al. to use aluminum induced layer exchange for thin-film solar cells, this paper will discuss the aluminum induced crystallization process itself as well as the implementation into workable solar cells. The record aluminum induced crystallization (AIC) solar cell today features an energy conversion efficiency of 8.5%, too low to be competitive with other PV technologies. The main problems and limitations as encountered today will be described. We believe that an energy conversion efficiency of 8.5% is not the limit of AIC solar cells. Different possible solutions to improve the AIC process as well as the resulting solar cells will be discussed together with our vision on the direction and future of AIC solar cell research.

Ultrathin SiO2 Films Grown by Atomic Layer Deposition Using Tris(dimethylamino)silane (TDMAS) and Ozone

Atomic layer deposition of SiO2 using tris(dimethylamino)silane and ozone were studied comprehensively. It was found that SiO2 grew linearly at different temperatures while the growth rate increased at higher temperatures. For thickness <3.5 nm, the direct tunneling current of the ALD SiO2 is comparable to that of thermally grown SiO2 when considering its equivalent oxide thickness (EOT). ALD could grow high-quality conformal SiO2 films on non-silicon substrates and on high aspect-ratio pores and nanostructures. The ALD SiO2 can be used as high-quality gate insulators for thin-film MOS transistors, and insulators for sensor structures and nanostructures on non-silicon substrates.

High-Quality Thin SiO2 Films Grown by Atomic Layer Deposition Using Tris(dimethylamino)silane (TDMAS) and Ozone

Atomic layer deposition of SiO2 using tris(dimethylamino)silane and ozone were studied comprehensively. It was found that SiO2 grew linearly at different temperatures while the growth rate increased at higher temperatures. For thickness <3.5 nm, the direct tunneling current of the ALD SiO2 is comparable to that of thermally grown SiO2 when considering its equivalent oxide thickness (EOT). The frequency dispersion and hysteresis behavior of the C-V curves of the ALD SiO2 films deposited at 100°C, 200°C, and 300°C are all very small in the thickness region of <3.5 nm, suggesting excellent interfacial quality. Based on analysis of mismatch between the films’ EOT and their physical thicknesses, the ALD SiO2 thin films are likely to be silicon-rich in composition. From the EOT point-of-view, the ALD SiO2 exhibits the same breakdown electrical field as that of the thermal oxide. From the physical thickness point-of-view, the breakdown electrical field is slightly lower than that of the thermal silicon oxide. The ALD SiO2 can be used as high-quality gate insulators for thin-film MOS transistors, and insulators for sensor structures and nanostructures on non-silicon substrates.

Swarm Intelligent Selection and Optimization of Machining System Parameters for Microchannel Fabrication in Medical Devices

Current technology trends in medical device industry calls for fabrication of massive arrays of microfeatures such as microchannels on to nonsilicon material substrates with high accuracy, superior precision, and high throughput. Microchannels are typical features used in medical devices for medication dosing into the human body, analyzing DNA arrays or cell cultures. In this study, the capabilities of machining systems for micro-end milling have been evaluated by conducting experiments, regression modeling, and response surface methodology. In machining experiments by using micromilling, arrays of microchannels are fabricated on aluminium and titanium plates, and the feature size and accuracy (width and depth) and surface roughness are measured. Multicriteria decision making for material and process parameters selection for desired accuracy is investigated by using particle swarm optimization (PSO) method, which is an evolutionary computation method inspired by genetic algorithms (GA). Appropriate regression models are utilized within the PSO and optimum selection of micromilling parameters; microchannel feature accuracy and surface roughness are performed. An analysis for optimal micromachining parameters in decision variable space is also conducted. This study demonstrates the advantages of evolutionary computing algorithms in micromilling decision making and process optimization investigations and can be expanded to other applications.

Metal induced crystallization of amorphous silicon for photovoltaic solar cells

A silicon thin-film technology could lead to less expensive modules by the use of less silicon material and by the implementation of monolithic module processes. A technology based on polycrystalline-silicon thin-films with a grain size between 1 μm and 1 mm (pc-Si), seems particularly promising since it combines the low-cost potential of a thin-film technology with the high efficiency potential of crystalline silicon. One of the possible approaches to fabricate pc-Si absorber layers is metal induced crystallization (MIC). For solar cell applications mainly aluminium is investigated as metal because 1) it forms a eutectic system with silicon instead of a silicide-metal system like e.g. Ni 2) only shallow level defects are formed in the forbidden bandgap of silicon and 3) a layer exchange process can be obtained in combination with a-Si. Aluminum induced crystallization (AIC) of a-Si on non-silicon substrates can results in grains with a preferential (100) orientation and a maximum grain sizes above 50 micrometer. These layers can act as seed layers for further epitaxial growth. Based on this two-step approach (AIC + epitaxial growth) we made solar cells with an energy conversion efficiency of 8%. Based on TEM, EBIC, SEM, defect etch and EBSD measurements we showed that the efficiency is nowadays mainly limited by the presence of electrical intragrain defects.

Thin-film monocrystalline-silicon solar cells made by a seed layer approach on glass-ceramic substrates

Solar modules made from thin-film crystalline-silicon layers of high quality on glass substrates could lower the price of photovoltaic electricity substantially. One way to create crystalline-silicon thin films on non-silicon substrates is to use the so-called “seed layer approach”, in which a thin crystalline-silicon seed layer is first created, followed by epitaxial thickening of this seed layer. In this paper, we present the first solar cell results obtained on 10-μm-thick monocrystalline-silicon (mono-Si) layers obtained by a seed layer approach on transparent glass-ceramic substrates. The seed layers were made using implant-induced separation and anodic bonding. These layers were then epitaxially thickened by thermal CVD. Simple solar cell structures without integrated light trapping features showed efficiencies of up to 7.5%. Compared to polycrystalline-silicon layers made by aluminum-induced crystallization of amorphous silicon and thermal CVD, the mono-Si layers have a much higher bulk diffusion lifetime.

Intragrain defects in polycrystalline silicon layers grown by aluminum-induced crystallization and epitaxy for thin-film solar cells

Polycrystalline silicon (pc-Si) thin-films with a grain size in the range of 0.1–100 μm grown on top of inexpensive substrates are economical materials for semiconductor devices such as transistors and solar cells and attract much attention nowadays. For pc-Si, grain size enlargement is thought to be an important parameter to improve material quality and therefore device performance. Aluminum-induced crystallization (AIC) of amorphous Si in combination with epitaxial growth allows achieving large-grained pc-Si layers on nonsilicon substrates. In this work, we made pc-Si layers with variable grain sizes by changing the crystallization temperature of the AIC process in order to see if larger grains indeed result in better solar cells. Solar cells based on these layers show a performance independent of the grain size. Defect etching and electron beam induced current (EBIC) measurements showed the presence of a high density of electrically active intragrain defects. We therefore consider them as the reason for the grain size independent device performance. Besides dislocations and stacking faults, also Σ3 boundaries were electrically active as shown by combining electron backscattered diffraction with EBIC measurements. The electrical activity of the defects is probably triggered by impurity decoration. Plasma hydrogenation changed the electrical behavior of the defects, as seen by photoluminescence, but the defects were not completely passivated as shown by EBIC measurements. In order to reveal the origin of the defects, cross section transmission electron microscopy measurements were done showing that the intragrain defects are already present in the AIC seed layer and get copied into the epitaxial layer during epitaxial growth. The same types of intragrain defects were found in layers made on different substrates (alumina ceramic, glass ceramic, and oxidized silicon wafer) from which we conclude that intragrain defects are not related to the relatively rough alumina ceramic substrates often used in combination with high temperature epitaxy. Further improvement of the material quality, and hence device performance, is therefore not simply achieved by increasing the grain size, but the intragrain quality of the material also needs to be taken into account. For pc-Si layers based on AIC and epitaxial growth, the seed layer has a crucial impact on the intragrain defect formation.

Development of a MEMS Electrical Inertia Micro-switch Based on Non-silicon Substrate

Based on non-silicon surface micromachining technology, a simple but reliable micro electro-mechanical system (MEMS) electrical inertia micro-switch with single sensitive direction and reverse impact protection is designed and fabricated on glass substrate. In this design, conjoined serpentine springs are used to fix and suspend the mobile electrode (mass) and blocks are used to protect the device against reverse impulse. The switch is laterally driven (i.e. its sensitive direction is parallel to the substrate). Fabrication is carried out by low-cost and convenient multi-layer electroplating technology. The relationship between threshold acceleration and mass thickness has been investigated by theoretical analysis and finite element analysis (FEA) simulation. After fabrication and packaging, micro-switches are tested by using drop weight. The results show that the threshold accelerations distribute between 58g and 72g, which basically fulfils the expected 60g; and the response time to 100g half-sine waved shock is in the order of 10–4 s, which is in agreement with simulation result.

Stamping-Based Planarization of Flexible Substrate for Low-Pressure UV Nanoimprint Lithography

Patterning flexible substrates in nano scale is an important and challenging issue in the fabrication of next-generation devices based on a non-silicon substrate. Step and Flash imprint lithography (S-FIL) which is a room temperature and low pressure process offers several important advantages, such as the use of a smaller and therefore cheaper stamp or the possibility of the overlay imprinting, as a transparent stamp is utilized. However, it is very difficult to perform S-FIL on a flexible substrate successfully due to the high waviness. The waviness of a flexible substrate is not a constant value in contrast to a rigid substrate. It depends on the imprint pressure applied onto the substrate. In this paper, in section two, the effect of the imprint pressure on the waviness of the surface of the flexible substrate is examined. It is proved that the waviness of the surface of the flexible substrate could not be reduced sufficiently to assure a successful imprint at low imprint pressures. In the third section, a method of patterning polymer substrates using ultra-violet nanoimprint lithography (UV-NIL) is presented. The method consists of two stages, stamping-based planarization and S-FIL. In stamping-based planarization, a planarization layer of transparent polymer is formed onto the flexible substrate. Waviness of the blank stamp (in this study, glass wafer) is transferred to the planarization layer. S-FIL is performed with the nanoimprint tool IMPRIO100 directly onto the planarization layer employing a 1 x 1 in. quartz stamp. Optical microscope and SEM images of the successfully imprinted patterns were also presented.

Formation of β-FeSi2 thin films on non-silicon substrates

β-FeSi2 films were prepared on non-silicon substrates by sputtering. The crystalline growth, stress induced cracks and adhesive ability to the substrate were investigated on substrate temperature and thermal expansion coefficient of substrate materials. It was found that crack formation in β-FeSi2 films was dependent on the thermal expansion coefficients of CaF2, MgO and quartz glass insulating materials. High-density cracks were observed from β-FeSi2 films on CaF2 and quartz glass substrates with large difference of the thermal expansion coefficient between β-FeSi2 film and substrate materials, and it was crack-free on MgO substrate with a thermal expansion coefficient close to that of β-FeSi2 films. Polycrystalline β-FeSi2 films grew on Mo, Ta, W, Fe and stainless steel (SS) substrates at low substrate temperature around 400 °C. There was no α-FeSi2 phase confirmed in the films. All the films had continuous structures without noticeable cracks even though they have different thermal expansion coefficients. Capacity–voltage measurements showed that β-FeSi2 films formed on SS substrates has n-type conductivity, with residual carrier concentrations of about 1.3∼6.4×1018 cm−3. Auger electron spectroscopy depth profile measurements identified homogeneous distribution of Fe and Si atoms in the film region, but with a large interface region between the film and the substrate.

Demonstration of Alternative Fabrication Techniques for Robust MEMS Device

This work describes efforts in the fabrication and testing of robust microelectromechanical systems (MEMS). Robustness is typically achieved by investigating non-silicon substrates and materials for MEMS fabrication. Some of the traditional MEMS fabrication techniques are applicable to robust MEMS, while other techniques are drawn from other technology areas, such as electronic packaging. The fabrication technologies appropriate for robust MEMS are illustrated through laminated polymer membrane based pressure sensor arrays. Each array uses a stainless steel substrate, a laminated polymer film as a suspended movable plate, and a fixed, surface micromachined back electrode of electroplated nickel. Over an applied pressure range from 0 to 34 kPa, the net capacitance change was approximately 0.14 pF. An important attribute of this design is that only the steel substrate and the pressure sensor inlet is exposed to the flow; i.e., the sensor is self-packaged.