Nominal Power Supply Research Articles

Characterization of electrically stressed power device metallization using nano-CT imaging

Power devices for automotive products are exposed to higher temperatures, currents, and voltages than common semiconductors. These devices are subject to large variations in the nominal power supply voltage. Power-Temperature Cycling (PTC) is an important reliability stress for power semiconductor devices, which addresses these specific load scenarios. It is known that PTC fails especially occur in the metallization of these power devices. Recent nano-CT imaging methods provide high-resolution 3D measurements on the relevant size scale suitable to spatially analyze these faults in detail. In this work, we demonstrate the suitability of the investigation method based on the study of various via-chain test structures previously stressed in the PTC and visually show the various defects that occurred in the process.

ELECTRICITY METER WITH THE FACILITY TO DETERMINE THE QUALITY OF THE ELECTRICITY SUPPLIED

Many areas of activity face the problem of electricity quality. At the same time, diagnosing the quality of the energy provided makes it possible to identify and remedy problems that have arisen in the system. Advanced signal processing techniques and the use of advanced systems allow for a complex analysis of the phenomenon. The paper presents an electricity meter equipped with an electricity quality analysis system. It was developed based on the Xilinx Artix-7 programmable logic matrix. A Digilent Arty A7 development board was used due to its design and experimentation facilities. The developed system determines the power consumed and the main elements that define the quality of electricity: harmonics and other deviations from the frequency of nominal power supply, flicker, voltage gaps, voltage variations, transient surge, temporary surge, etc. The possibility of using an embedded system equipped with the Microblaze soft microprocessor, the existence of a 12-bit analog-digital converter and the maximum sampling frequency of 1 MSPS and the possibility of assisted design allows to obtain a measurement system with superior characteristics. The results obtained and the experiments carried out confirm the expected performance for the electricity meter.

High accuracy potentiostat with wide dynamic range and linearity

Electrochemical measurement require potentiostat to ensure the operational stability during the sensing and conversion of the sensor signals. This article presents a potentiostat circuit with high linearity and accuracy bidirectional current readout circuit for a wide dynamic current range. A current conveyor circuit with a wide current range from ±50 nA to ±400 μA is constructed by combining a low-noise current mirror based OTA and a regulated current mirror employing accurate and linear output characteristics. The potentiostat is designed in 0.18 μm TSMC technology with ± 0.9 V nominal power supply, and the results obtained are based on simulation and performed with CadenceTM tools. The potentiostat circuit achieves a minimum detectable current of 1 nA within current range of ±400 μA. The detectable current range is 112 dB with R2 linearity of 0.999999993 and maximum error of 1.3%. The input referred noise of the current conveyor is 24.48 fA/Hz @1 kHz, and integrated referred noise is 0.912 pA within 0.01 Hz - 1 kHz bandwidth. The static power consumption of the potentiostat circuit is 1.993 mW. The control amplifier and the current readout circuit consume 1.98 mW and 13 μW, respectively. The proposed circuit is capable of providing low noise and high accuracy current measurement with low power consumption and highly linear output characteristics.

Analysis of technical and operational characteristics of turning-and-shunting door opening mechanism of electric public transport

One of the most important problems occurring while designing public transport vehicles consists in providing an effective control of the door opening systems. The methods of carrying out the investigations presented in the paper include structural and kinematic analysis of the door opening mechanisms and simulation of their operation in applied software. The paper analyses the design and operational peculiarities of the turning-and-shunting mechanism of door opening of electric public transport. The corresponding design of the mechanism is proposed. It is suggested to be driven by pneumatic drive. The simplified diagram of the mechanism is constructed. Structural and kinematic analysis of the mechanism is performed, and the analytical dependencies for describing the motion of its links during the door opening/closing are derived. The main kinematic parameters of the studied mechanism are investigated on the basis of the derived analytical dependencies in MathCAD software, as well as by means of simulating the motion of the solid-state model of the mechanism designed in SolidWorks software. The conclusions about the agreement of the results of theoretical investigations performed on the basis of numerical solving the obtained motion equations and of the virtual experiment (motion simulation in SolidWorks software) are drawn. The analysis of energy efficiency of the investigated turning-and-shunting door opening mechanism of electric public transport is carried out. Prescribing the resistance force acting on the door leaf and calculating the corresponding door motion speed during its closing, the dependency of the nominal power supply of the mechanism drive as a function of corresponding generalized coordinates was deduced. Analyzing the obtained results, the authors have established that the necessary nominal power of the turning-and-shunting mechanism drive is almost twice larger than the necessary nominal power of the widely used leaning-and-shunting mechanism. Further investigations on the subject of the paper can be performed in the direction of developing different control systems providing safe and reliable operation of the considered door opening mechanism driven be electric and pneumatic actuators.

PWM Inverter Drive for Modified Single Phase Induction Motors

This paper starts to look at the single phase induction machine which is a large consumer of domestic power supply with the goal of improving its operation. The existing capacitor-run single phase induction motor exhibits a significant level of torque pulsations during starting time and at steady state. This situation gives rise to noise and vibration in the machine. As part of efforts to mitigate these problems, an open loop two phase inverter drive strategy was developed and implemented in MATLAB/Simulink to reduce undesirable pulsations. Simulation results clearly show the superiority of motor performance under the proposed strategy when compared to motor performance under nominal power supply. Torque pulsations are eliminated at steady state with the consequence of reduced noise and heat loss to the environment. The motor is observed to develop significantly higher starting torque and its reliability is significantly increased as the strategy eliminates the need for capacitors and centrifugal switch associated with these motors.

A Fully Integrated Multistage Cross-Coupled Voltage Multiplier With No Reversion Power Loss in a Standard CMOS Process

This brief presents a fully integrated cross-coupled voltage multiplier for boosting dc-to-dc converter applications. The proposed design applies a new structure of cross-coupled voltage doubler (CCVD) and a clock scheme that eliminates all of the reversion power loss and increases the power efficiency (PE). In addition, this design is scalable to multiple-stage voltage doubler (voltage multiplier) as the maximum gate-to-source/drain or drain-to-source voltage does not exceed the nominal power supply $V_\mathrm{dd}$ . As a result, such a design is compatible with the standard CMOS process without any overstress voltage. The proposed single-stage CCVD and three-stage cross-coupled voltage multiplier are implemented in 0.13- $\mu\text{m}$ IBM CMOS process with maximum PE values of 88.16% and 80.2%, respectively. The maximum voltage conversion efficiency reaches 99.8% under the supply voltage of 1.2 V.

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

Routing multiplexers based on pass-transistors or transmission gates are an essential components in many digital integrated circuits. However, whatever structure is employed, CMOS multiplexers have two major limitations: 1) their delay is linearly related to the input size; 2) their performance degrades seriously when operated in near-Vt regime. Resistive Random Access Memory (RRAM) technology brings opportunities of overcoming these limitations by exploiting the properties of RRAMs and associated programming structures. In this paper, we propose new one-level, two-level and tree-like multiplexers circuit designs using 4T(ransistors)1R(RAM) elements and we compare them to naive one-level multiplexers. We consider the main physical design aspects associated with 4T1R-based multiplexers, such as the layout implications using a 7 nm FinFET technology, and the co-integration of low-voltage nominal power supply and high-voltage programming supply. Electrical simulations show that using a 7 nm FinFET transistor technology, the proposed 4T1R-based multiplexers reduce delay by 2x and energy by 2.8x over naive 4T1R and 2T1R counterparts. At nominal working voltage, considering an input size ranging from 2 to 50, the proposed 4T1R-based multiplexers reduces Area-Delay and Power-Delay products by 2.6x and 3.8x respectively, as compared to best CMOS multiplexers. In the nearVt regime, the proposed 4T1R-based multiplexer demonstrates 2x larger delay efficiency over the best CMOS multiplexer. The proposed 4T1R-based multiplexers operating at near-Vt regime can still achieve up to 22% delay improvement when compared to best CMOS multiplexers working at nominal voltage.

A 10 Gbps differential low-power loss of signal detector for AC-coupled serial transceivers in 28 nm CMOS technology

This work presents a differential low-power 10Gbps loss of signal (LOS) detector for high-speed AC-coupled serial transceivers. The detector is designed in 28nm CMOS technology. It includes a novel comparator circuit that compares a differential input signal to a differential reference voltage with minimal sensitivity to the common mode voltage of the input signal. The LOS detector is capable of properly detecting a valid signal that has an external eye opening as low as 85mV and an internal eye opening as low as 36mV at the input pads. It asserts LOS if the external eye opening is below 50mV. It consumes 113uW from a 0.9V nominal power supply at 10Gbps date rate and properly asserts an LOS state in 25.5nS at typical corner operation. It occupies 0.00169mm2 of area. In simulations that include metal parasitic resistance and capacitance, the detector is shown to withstand process, voltage and temperature (PVT) variations and satisfy the commercial operating temperature range. The design and layout of the system were implemented in Synopsys Custom Designer using 28nm CMOS device models.

Cooling performance measurement of the reverse application of a coaxial free-piston Stirling engine

The free-piston Stirling machine has been used as either thermal engine, cryocooler, or heat pump, due to its compact structure, high efficiency, and reliability. A compact engine-refrigerator dual-functional coaxial free-piston Stirling engine was designed and fabricated. It could output 1000 W electricity power with a conversation rate of 20%, when the hot end was heated up to 530°C and the cold end cooled by water which was heated from room temperature to 65°C. The engine was reversely operated as a refrigerator without any modification, and its cooling performance was measured at different input power. The results indicate that, a none-load cooling temperature 142.4 K was obtained at a maximum power supply voltage of 300 VAC (50 Hz), and 193.1 K was reached at a minimum input power of 60 VAC (50 Hz). For a nominal power supply 220 VAC@50 Hz (i.e., 716.8 W), the cooling power increases from 2.4 to 276 W when the temperature at the cold head changes from 156.6 to 203 K. The relative Carnot coefficient of performance of the Stirling unit as a cooler is 18.6% at 203 K.

A Nonvolatile Sense Amplifier Flip-Flop Using Programmable Metallization Cells

In this work, a zero-leakage nonvolatile flip-flop architecture based on a differential CMOS sense-amplifier flip-flop is presented. The flip-flop stores data in complimentarily programmed resistive memory devices during inactive period while power supply is turned off and then restores the data to flip-flop outputs once power supply is turned back on. The resistive memory technology considered here are known as programmable metallization cell (PMC) that switches via metal ion transport within a solid electrolyte. Simulations of the proposed circuit using a PMC compact model fitted to experimental data are performed to estimate the reliability of the read operation and energy consumption for both nominal and sub-threshold power supply regimes. Energy and reliability tradeoffs in the choice of the programmable low resistance state are also discussed. The proposed sense amplifier- based design is more compact than previously reported master-slave latch based nonvolatile designs and presents a modified data restore circuit for more robust read operation at subthreshold voltage supply levels. The wide margin between high and low resistance states of the PMC devices further improves robustness of the flip-flop. Lastly, possible extension of this architecture for low power logic computation application is briefly discussed.

Data aacquisition system for rape growth environment based on WSN

In view of the traditional acquisition means of crop growth environment data being poor real-time, high labor intensity, and considering the high cost, poor openability, of deployment of micro automatic weather stations and commercial Zigbee products, we have designed and realized a rape growth environment data acquisition system based on WSN. putting forward the lightweight energy-aware routing protocol CLFP, and giving the related design method of hardware and software. The simulation and field experiment, have shown that the temperature acquisition system accuracy can reach 0.01 ℃, humidity measurement precision is up to ± 5%, intensity collection range of light is up to 1~65 535 lx, data transmission routes can be up to 36, which can satisfy the high measurement requirements for agricultural environmental data. with the nominal power supply, the real effective working cycle of the system is more than 142 days, by taking the AT89C51 and nRF2401 as the basic hardware platform, the system is of low cost, which contributes to its large-scale deployment and application.

Associative memory architecture for word-parallel smallest Euclidean distance search using distance mapping into clock-number domain

A scalable word-parallel associative memory for smallest Euclidean distance (ED) search is presented. Due to the applied concept of distance to clock-number mapping, the reported architecture is digital in nature and scalable to advanced technology. Furthermore, the reference data of feature vectors can be scaled in principle to any vector dimension and number. Handling of the numerical complexity of the ED without large consumption of Silicon area is achieved by an area-efficient circuit, which uses the same adder for absolute-difference calculation of vector components and subsequent square calculation by sequential addition of partial products. Additionally, a clock-number minimization algorithm is proposed to significantly reduce the clock-number needed for the search when the smallest ED is a large value. The concept of the proposed architecture has been experimentally verified by measurement results from real chips fabricated in a 180 nm CMOS technology, in which the architecture is configured for parallel smallest ED search among 32 reference vectors with each vector having 16 8-bit elements. For the application example of codebook-based data compression, the fabricated test chip achieved 1.19 µs average search time, 5.77 µs worst-case search time and low power consumption of 8.75 mW at the maximum clock frequency of 47 MHz and nominal power supply voltage Vdd = 1.8 V. At reduced power supply voltage Vdd = 1.2 V, a smaller power consumption of 2.80 mW at an also smaller maximum clock frequency of 24 MHz is measured. In comparison to previous analog–digital architecture, a reduction of the normalized power-delay product per matching operation by about a factor 1.6 at Vdd = 1.8 V (about factor 2.5 at Vdd = 1.2 V) is obtained with best-case data for the analog–digital architecture and average-case data for the proposed fully-digital architecture.

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

A power-efficient 12-bit 40-MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two opamp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC's performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.43 to +0.48 LSB and −1.62 to +1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure-of-merit (FOM) of 0.63 pJ per conversion-step.

Thermoeconomic Approach and Optimization of a Solar Thermal Power Plant

In the present study, a specific and simple second law based exergoeconomic model with instant access to the production costs is introduced. The model is generalized for a case study of Shiraz solar thermal power plant with parabolic collectors for nominal power supply of 500 kW. Its applications include the evaluation of utility costs such as products or supplies of production plant, the energy costs between process operations of an energy converter such as production of an industry. Also attempt is made to minimize objective function including investment cost of the equipments and cost of exergy destruction for finding optimum operating condition for such plant.

Time Difference Amplifier with Robust Gain Using Closed-Loop Control

This paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time difference. Cross coupled chains of variable delay cells with the same number of stages are applicable for TDA, and the gain is adjusted via the closed-loop control. The TDA was fabricated using 65 nm CMOS and the measurement results show that the time difference gain is 4.78 at a nominal power supply while the designed gain is 4.0. The gain is stable enough to be less than 1.4% gain shift under ±10% power supply voltage fluctuation.

Single-Event Effects on Combinational Logic Circuits Operating at Ultra-Low Power

The minimum laser energy required to cause sustained harmonic oscillations in a 201-stage ring oscillator varies little with increasing power supply voltage when operating in the subthreshold region. These small changes in threshold laser energy in the subthreshold region suggest that the cross-section curves as a function of power supply voltage remain relatively constant. Simulations show that the minimum pulsewidth required to generate higher-order oscillations decreases as operating voltage increases. Single-event transients are wider when circuits are operating in the subthreshold region than when operating at the nominal power supply voltages. Narrower single-event transients result for strikes on PMOS transistors as compared to those for strikes on NMOS devices in the subthreshold region; the opposite is observed when circuits are operating at the nominal power supply voltages.

A 1-GHz, multibit, continuous-time, delta–sigma ADC for Gigabit Ethernet

In this work the design of a continuous-time ΔΣ modulator for Gigabit Ethernet applications is presented. The input bandwidth and oversampling ratio are, respectively, 62.5MHz and 8, resulting in a clock frequency of 1GHz. It was designed and implemented in a standard 90nm CMOS technology. The active area of the modulator measures 0.0207mm2. It consists of a loop filter based on RC-opamp integrators and a 3-bit quantizer which includes a data weighted averaging scrambler. A digital tuning scheme to deal with process variations has also been included. System level simulations including several non-ideal effects have been carried out in order to determine in detail the performance of the converter. Experimental results show a resolution of 7.1 effective bits, and a power consumption of 10.8mW from a nominal power supply of 1V.

A Stress-Relaxed Negative Voltage-Level Converter

In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-mum triple-well standard CMOS technology, using double-gate-oxide-thickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of -3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported

2.5 V 43–45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family

An alternative design approach for implementing high-speed digital and mixed-signal circuits is proposed. It is based on a family of low-voltage logic gates with reduced transistor stacking compared to series-gated emitter-coupled logic. It includes a latch, an XOR gate, and a MUX with mutually compatible interfaces. Topologies and characteristics of the individual gates are discussed. Closed-form propagation delay expressions are introduced and verified with simulations. The proposed design style was used to implement a 43-45 Gb/s CDR circuit with a 600MHz locking range and a 55 Gb/s PRBS generator with a 27-1 sequence length. The circuits were fabricated in a SiGe BiCMOS technology with fT=120 GHz. Corresponding measurement results validate the proposed design style and establish it as a viable alternative to emitter-coupled logic in high-speed applications. Both circuits operate from a 2.5 V nominal power supply and consume 650 mW and 550 mW, respectively

Intravascular pressure monitoring system

Abstract Monitoring of blood pressure and pulse rate offers diagnostical and therapeutical opportunities in hypertension disease and arrhythmia. An intravascular pressure monitoring system is presented consisting of an implantable silicone capsule, which can be placed in the arterial system via a guiding catheter. The capsule contains a single transponder chip with a monolithically integrated capacitive pressure sensor and a ferrite-based antenna. The chip operates at a nominal power supply voltage of 3 V and dissipates less than 450 μW at a clock rate of 6.78 MHz.