Noise-canceling Receiver Research Articles

Double-Conversion, Noise-Cancelling Receivers Using Modulated LNTAs and Double-Layer Passive Mixers for Concurrent Signal Reception With Tuned RF Interface

A double-conversion, noise-cancelling receiver architecture is presented that consists of a double-layer mixer-first branch and two quadrature-modulated LNTA branches. The two layers of passive mixing in the mixer-first branch up-convert the low-pass, baseband impedance and create concurrent, narrowband impedance matching at (F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LO</sub> ±F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IF</sub> ), as well as concurrently receive signals around these two RF carriers while rejecting spurious responses without using any IF filters. To improve the noise performance, quadrature-modulated LNTA branches are incorporated to allow frequency-translational, noise cancellation for better receiver sensitivity. Double conversion is achieved in the LNTA branches by periodically varying the LNTA transconductance and current-mode, passive mixing. A generalized, linear time-varying (LTV) analysis of the receiver is presented and verified with behavioral-model simulation results.

A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture

A modified noise/nonlinearity cancellation low-noise transconductance amplifier (LNTA) based on an inductively degenerated common-source stage is proposed to improve linearity. The linearity of the proposed LNTA is analyzed using the Volterra series yielding closed-form equations for the third-order input intercept point (IIP3) that shows excellent matching with the simulation results. The derived equations for noise figure (NF) and IIP3 are simple enough to be used for design optimization. Calculations and simulation results show that the proposed LNTA is more linear than a conventional one, while NF approximately remains unchanged. Another feature of the proposed noise-canceling LNTA is that no additional baseband recombination stage is needed, leading to reduced complexity in the receiver baseband stage. The NF and out-of-band (OOB) IIP3 of the receiver is about 3.3 dB and more than 20 dBm, respectively. The receiver consumes 10.5 mA from 1.8-V supply voltage. The current consumption of the LO divider is 6.5 mA from a dedicated 1-V supply voltage.

A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications

In this article, we propose a baseband noise-canceling receiver architecture to increase in-band linearity. A key feature of the architecture is that all active circuits are in baseband, including the low-noise transconductance amplifier (LNTA). The LNTA operating at baseband frequencies allows the use of feedback to increase the linearity. This article analyzes a tradeoff that exists between in-band linearity and noise in mixer-first receivers and shows how the proposed architecture breaks such tradeoff. The receiver targets high IF bandwidths, enabled by a transimpedance amplifier (TIA) composed of an OpAmp using only inverters. This article describes the stabilization mechanism of this OpAmp with a unity-gain bandwidth (UGB) of 7.6 GHz. The receiver is fabricated in 22-nm FDSOI CMOS. The measured results show an in-band IIP3 of > 9 dBm for an IF bandwidth of 175 MHz with sub-5-dB noise figure (NF) across 1-6-GHz local oscillator (LO) frequencies.

Design of a SAW-less, noise-canceling receiver using an LPTV analysis of a general system with an arbitrary number of N-path filters

This paper, first, presents a Linear Periodically Time-Variant (LPTV) analysis of a general system with an arbitrary number of n-path filters, that the results of mathematical derivations are verified through simulation. Then, a noise-canceling receiver is presented with 3 stages of the 8-path filter. In the structure of this receiver, two filters are used for noise-canceling, and the third filter is used as a Miller bandpass filter to increases the selectivity. The proposed circuit is designed with 65 nm RF CMOS technology and the simulation results show > 44 dB gain, 3–4.5 dB NF, and 0 dBm out-of-band IIP3 at the 50 MHz offset, while in 0.3–3 GHz functional frequency, consuming just 15.52mW of power.

An Out-of-Band IM3 Cancellation Technique Using a Baseband Auxiliary Path in Wideband LNTA-Based Receivers

An out-of-band (OB) third-order intermodulation (IM3) cancellation technique is proposed and analyzed. By exploiting a baseband (BB) auxiliary path (AP) with high-pass feature, the in-band desired signal, and OB interferers are split. OB IM3 products are then reconstructed in the AP and cancelled in the BB. The approach is implemented using a 65-nm CMOS 0.5- to 2.5-GHz frequency-translational noise-cancelling receiver, and it achieves 8.8-MHz BB bandwidth, 40-dB gain, 3.3-dB noise figure, 5 dBm OB third-order input intercept points (IIP3), and −6.5-dBm OB B1dB without IM3 cancellation with 36 mW at 1-GHz local oscillator (LO) frequency and 1.2-V supply. After IM3 cancellation, the effective OB-IIP3 has increased to 32.5 dBm with an extra 34 mW for narrowband interferers (two tones). For wideband interferers, 18.8-dB cancellation is demonstrated over 10 MHz with two −15-dBm modulated interferers. The LO leakage is −92 and −88 dBm at 1- and 2-GHz LO, respectively. This technique can achieve both high OB linearity and good LO isolation.

A Wideband Noise-Cancelling Receiver Front-End Using a Linearized Transconductor

A Wideband Noise-Cancelling Receiver Front-End Using a Linearized Transconductor

A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers

By employing two passive-mixer-based downconversion paths, a recently proposed noise cancelling receiver achieves a low-noise figure and tolerates most out-of-band blockers up to 0 dBm with little performance degradation. However, like most wideband passive-mixer-based designs, the architecture is far less tolerant of harmonic blockers, that is blockers located at or around precise integer multiples of the LO frequency. These blockers are problematic because they are downconverted inside the bandwidth of the baseband TIAs and, so, experience significant on-chip voltage gain. This work presents an enhanced noise-cancelling architecture that prevents harmonic blockers experiencing large on-chip gain, thereby boosting the receiver's resilience to such blockers. It will be shown that separate techniques are required for the voltage-driven main path and the current-driven auxiliary path. To validated these ideas, single-ended and fully-differential prototypes were fabricated in 28 nm silicon.

A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching

This paper presents an inductor-less frequency selective input match wireless receiver front-end utilizing noise cancellation, operational from 0.7 to 3.8 GHz. The main path of the receiver consists of a high input impedance transconductance stage where the output is down-converted to baseband by current mode passive mixers, and then amplified to voltage by a transimpedance amplifier. The output voltage is converted into a current and frequency up-converted by a second set of transconductance stage and mixer. This current is then fed back to the input of the main path, reducing the input impedance, providing input match by means of negative feedback. An auxiliary path with digitally controllable gain is also introduced to cancel the noise of the main path while maintaining high linearity. The chip prototype is fabricated in a 65 nm CMOS process and occupies an active area of 0.15 mm $^2$ . It achieves a noise figure between 1.6 dB and 3.2 dB depending on the frequency of operation, and an out-of-band IIP2 and IIP3 better than +75 dBm and +1 dBm, respectively. The chip is supplied by 1.2 V and consumes 22.8–34.9 mA.

An LTV Analysis of the Frequency Translational Noise-Cancelling Receiver

The recently proposed Frequency-Translational Noise-Cancelling receiver demonstrates exceptional out-of-band linearity, a low noise factor, and wideband operation. Fundamental to the receiver's performance is the use of two passive-mixer-based downconversion paths, which delays noise-cancelling until after baseband filtering. As a result, voltage gain at blocker frequencies can be avoided, but the benefits of noise cancelling (i.e., wideband operation and low noise) can be retained. Although a simplified LTI analysis is sufficient to understanding the basic noise properties of the system, such an analysis cannot yield accurate closed-form expressions because it neglects the many signal and noise folding terms introduced by the two passive mixers. In this work, a complete LTV analysis is presented, which accurately captures both the gain and noise performance of the noise-cancelling receiver. Simulation results verify the analysis.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.