NoC Structure Research Articles

Buffer Sizing for Multimedia Flows in Packet-Switching NoCs

Wormhole packet switching, used in many NoC designs, introduces jitter. This may produce violations of application deadlines. Several works in the literature propose stream workload models, and techniques for buffer sizing. These works do not consider the concurrency between different flows, or the NoC model is too abstract, masking the jitter introduced by data packaging and router processing. One technique to deal with jitter is to introduce a decoupling buffer (D-buffer) on the target IP. This buffer receives data from the NoC with jitter, while the target IP consumes data from this buffer at the application rate, without jitter. Two problems must be solved to implement D-buffers: (i) which size must the buffer have? (ii) how much time should be expected before data consumption starts (threshold)? This work proposes a general method to define D-buffer size and threshold, considering the influence of packaging, arbitration, routing and concurrency between flows. A traffic model for stream applications is detailed and used to characterize jitter sources in wormhole packet switching. Experimental results demonstrate the impact on multimedia flows with fixed and variable packet sizes (from real traffic traces). Simple traffic models employing constant frame sizes result in small D-buffers. On the other hand, employing multimedia frames from application traces (i.e. real application data) increases buffer size and threshold while still suppressing jitter. Another parameter analyzed in the paper is the percentage of deadline violations as a function of D-buffer size. The method guarantees throughput with no deadline violation and does not modify the NoC structure. The cost of adding such D-buffers is an increased latency and extra silicon area.

Logophoric Centers as Antecedents of NOC PRO: Evidence from Turkish Subject Infinitives

This paper questions the mechanism behind the control structure observed in subject infinitival clauses in Turkish. After comparing the main points of the proposals in the Movement Theory of Control in Boeckx, Hornstein, and Nunes (2010), pragmatics based Non-Obligatory Control analysis in Landau (2013), and the UPro Approach in McFadden and Sundaresan (2016), I conclude with the claim that these are logophoric center sensitive NOC structures.

The Design and Implementation of Fast-Path Architecture for IPv6 Control Router

In view of the difficulties of the current router architecture such as capacity, scalability, and power consumption, a fast-path architecture of IPv6 router suitable for parallel processing is proposed. The fast-path architecture of IPv6 router is designed and implemented using NoC structure. Thereby, a parallel processing structure of IP packets combining the distributed IP address lookup and the parallel IP packet switching is implemented. It is convenient to replace the search algorithm and to expand the hardware scale, and it can improve the overall performance of the router effectively.

Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels

Shorter global interconnects enable 3D NoC structures to offer higher performance, improved packaging density, and lower interconnect power consumption to CMPs and SoCs compared to their 2D counterparts. However, substantial challenges such as high peak temperatures, power densities and area footprints of vertical interconnects in each layer cannot be ignored. In this paper, a power and area efficient 3D NoC architecture based on power-aware Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a dynamically self-configurable BBVC enables a system to benefit from low-latency nature of the vertical interconnects. In addition, based on the GALS implementation approach of the proposed channels, a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication is introduced. Simulation results show that the proposed architecture can reduce up to 47% through-silicon via (TSV) area footprint and up to 18% NoC power consumption with a slight performance degradation compared to a typical Symmetric 3D NoC.

Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology

This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6% on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0% and 34.0%, respectively.

A GALS Infrastructure for a Massively Parallel Multiprocessor

This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons. Every node of the design comprises 20 ARM9 cores, a memory interface, a multicast router, and two NoC structures for communicating between internal cores and the environment. The NoCs are asynchronous; the cores and RAM interfaces are synchronous. This GALS approach decouples clocking concerns for different parts of the die, leading to greater power efficiency.