No-flow Underfill Materials Research Articles

Effect of the Thermomechanical Properties of No-Flow Underfill Materials on Interconnect Reliability

The demands on flip chip packaging are increasing as the requirement for miniaturization and thinner silicon chips rises. In encapsulating flip chip packages it is important to not only maintain the mountability, but also to control the warpage of the package. In this paper, three types of underfill material with different thermomechanical properties are prepared. The requirements for achieving both longer interconnect life and the mountability with lower warpage are investigated. Underfill material with higher Young's modulus shows a longer interconnect life. From the results of failure analysis after thermal cycling, cracking at the edges of the bumps is observed. It is found from finite element analysis that underfill material with higher Young's modulus can effectively reduce the strain accumulating inside the bump. Underfill material with a low coefficient of thermal expansion reduces warpage after chip assembly. Therefore, optimization of both Young's modulus and the coefficient of thermal expansion of the underfill material are essential in order to achieve higher interconnect reliability while maintaining higher mountability.

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

Effect of Nano-Particles on Heterogeneous Void Nucleation in No-Flow Underfill Materials

The large number of voids induced by the thermal effect from solder reflow process is one of the technical challenges for flip chip package techniques typically with no-flow underfills. The underfill voids could extensively reduce the life cycle in thermal cyclic test. This paper reviewed classical heterogeneous bubble nucleation theories to model voids nucleation occurring on the phase boundary of solid solder and liquidus underfill to control the nucleation during flip chip assembly process using no-flow underfill materials. On the heterogeneous voids nucleation, the properties of nucleation sites (such as density and surface tension) that determine void formation were explored using nano-sized fillers. Thus, this experiment investigated the effect of nano-sized fillers, which are potential nucleation sites in the no-flow underfill material, on the void formation by changing the nano-sized filler type and concentration. Eventually, we proposed a formulation guideline of no-flow underfill materials using nano-sized fillers to effectively prevent the underfill voiding during flip chip assembly process.

High Yield, Near Void-Free Assembly Process of a Flip Chip in Package Using No-Flow Underfill

The advanced assembly process for a flip chip in package (FCIP) using no-flow underfill material presents challenges with high I/O density (over 3000 I/O) and fine-pitch (down to 150 μm) interconnect applications because it has narrowed the feasible assembly process window for achieving robust interconnect yield. In spite of such challenges, a high yield, nearly void-free assembly process has been achieved in the past research using commercial no-flow underfill material with a high I/O, fine pitch FCIP. The initial void area (approximately 7% ) could cause early failures such solders fatigue cracking or solder bridging in thermal reliability. Therefore, this study reviewed a classical bubble nucleation theory to predict the conditions of underfill void nucleation in the no flow assembly process. Based on the models prediction, systematic experiments were designed to eliminate underfill voiding using parametric studies. First, a void formation study investigated the effect of reflow parameter on underfill voiding and found process conditions of void-free assembly with robust interconnections. Second, a void formation characterization validated the determined reflow conditions to achieve a high yield and void-free assembly process, and the stability of assembly process using a large scale of assemblies respectively. This paper presents systematic studies into void formation study and void formation characterization through the use of structured experimentation which was designed to achieve a high yield, void-free assembly process leveraging a void formation model based on classical bubble nucleation theory. Indeed, the theoretical models were in good agreement with experimental results.

Evaluation of Cu/Sn-Cu Bump Bonding Processes for 3D Integration Using a Fluxing Adhesive

The study of copper-based bump structures for interconnects in 3D integration applications has been ongoing for several years. Typically, an array of Cu bumps is bonded to an array of Sn-capped Cu bumps or another Cu bump array using a thermocompression bonding process. These processes rely on high pressures and temperatures to facilitate bonding between the bump arrays. In order for this bonding to take place, some method of oxide removal is normally required for the Cu and/or Cu/Sn bump surfaces before bonding. A number of different methods have been investigated by a number of groups, including chemical cleaning, plasma cleaning, self-assembled monolayers, and no-flow underfill (NUF) materials. The use of NUFs is particularly intriguing, since these materials can be formulated with fluxing agents which could reduce surface oxides on Cu and Sn and can be deposited immediately prior to the thermocompression bonding process. In addition, the material provides a protective encapsulant to the interconnect array, protecting it from environmental damage and adding mechanical strength to the assembly. We will present the results of a study to evaluate new fluxing NUF materials in thermocompression bonding processes on full area array test devices with 25 micron bump pitch. The test devices are fabricated with either Cu or Cu/Sn bumps to provide two different bonding options (Cu to Cu or Cu/Sn to Cu). We will compare the NUF bonding process and resulting bonded interfaces to assemblies fabricated using our standard bonding processes, which rely on both chemical and plasma pretreatment processes to prepare the bump arrays before bonding. Mechanical and electrical data will be used to compare the two bonding processes, as well as SEM cross-section analysis of the bonded interfaces.

Void Formation Mechanism of Flip Chip in Package Using No-Flow Underfill

This paper investigates the void formation mechanism induced by chemical interaction between eutectic solder (Sn63/Pb37) wetting and no-flow underfill material curing during flip chip in package assembly. During the process, low weight molecular components, such as fluxing agents and water molecules, could be induced by the chemical interaction between solder wetting and underfill curing when these components are heated to melt and cure, respectively. The low weight molecular components become volatile with exposure to temperatures above their boiling points; this was found to be the main source of the extensively formed underfill voiding. This mechanism of chemically and thermally induced voids was explained using void formation study, differential scanning calorimetry thermogram comparison, and gas chromatography and mass spectroscopy chemical composition identification on the suggested chemical reaction formula. This finding can enhance understanding of the mechanism that drives no-flow underfill voiding and can develop a void-free flip chip assembly process using no-flow underfill material for cost effective and high performance electronics packaging applications. Furthermore, this study provides the design guideline to develop an advanced no-flow underfill having high performance at high temperature range for the lead-free application.

Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 mum) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite of such challenges, a high yield, reliable assembly process (>99.99%) has been achieved using commercial no-flow underfill material with a high I/O, fine-pitch FCIP. This has been obtained using design of experiments with physical interpretation techniques. Statistical analysis determined what assembly conditions should be used in order to achieve robust interconnects without disrupting the FCIP interconnect structure. However, the resulting high yield process had the side effect of causing a large number of voids in the FCIP assemblies. Parametric studies were conducted to develop assembly process conditions that would minimize the number of voids in the FCIP induced by thermal effects. This work has resulted in a significant reduction in the number of underfill voids. This paper presents systematic studies into yield characterization, void formation characterization, and void reduction through the use of structured experimentation which was designed to improve assembly yield and to minimize the number of voids, respectively, in FCIP assemblies.

Theoretical Modeling and Prediction of Delamination in Flip Chip Assemblies With Nanofilled No-Flow Underfill Materials

The occurrence of passivation-underfill interfacial delamination is detrimental to the reliability of the flip chip assembly as it can result in the premature cracking of the solder bumps. In this paper, the propagation of delamination in a nanofilled no-flow underfill material from the chip passivation in flip chip assemblies has been assessed under accelerated thermal shock testing. A theoretical model of the flip chip assembly has been developed, and the delamination occurring at the silicon nitride (SiN)–underfill interface has been studied under monotonic as well as thermomechanical fatigue loading. Using empirical models for delamination propagation, the growth of delamination under monotonic as well as thermomechanical fatigue loading in a flip chip assembly has been predicted. These predictions agree well with the thermal shock cycling experimental data. The agreement between the theoretical predictions and experimental data suggests that the models and the methodology developed in this work can be used to design flip chip assemblies with nanofillled no-flow underfill materials against interfacial delamination.

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.

Experimental Characterization of Monotonic and Fatigue Delamination of Novel Underfill Materials

No-flow underfill materials reduce assembly processing steps and can potentially be used in fine-pitch flip chip on organic board assemblies. Such no-flow underfills, when filled with nano-scale fillers, can significantly enhance the solder bump reliability, if the underfills do not prematurely delaminate or crack. Therefore, it is necessary to understand the risk of underfill delamination during assembly and during further thermal excursions. In this paper, the interface between silicon nitride (SiN) passivation and a nano-filled underfill (NFU) material is characterized under monotonic as well as thermo-mechanical fatigue loading, and fracture parameters have been obtained from such experimental characterization. The passivation-underfill interfacial delamination propagation under monotonic loading has been studied through a fixtureless residual stress induced decohesion (RSID) test. The propagation of interfacial delamination under thermo-mechanical fatigue loading has been studied using sandwiched assemblies and a model for delamination propagation has been developed. The characterization results obtained from this work can be used to assess the delamination propagation in flip-chip assemblies. Though the methods presented in this paper have been applied to nano-filled, no-flow underfill materials, their application is not limited to such materials or material interfaces.

Thermomechanical and viscoelastic behavior of a no-flow underfill material for flip-chip applications

No-flow underfill is an alternative material technology for packaging high-speed flip-chip assemblies in microelectronics industry. In this study, the thermal expansion behavior of a cured no-flow underfill material was examined by thermomechanical analysis (TMA), and the dynamic mechanical behavior was investigated by dynamic mechanical analysis (DMA) at a fixed frequency of 1 Hz. In addition, because the no-flow underfill material is polymer-based and its mechanical properties are influenced by both temperature and time, it is important to consider its viscoelastic behavior. This was accomplished by conducting the time–temperature superposition (TTS) experiments using DMA. From the TTS results, master curves were constructed for both the storage ( E′) and the loss moduli ( E″) as a function of frequency at a pre-selected reference temperature. The shift factors along the frequency axis were also determined as a function of temperature, and they can be fitted using the Williams–Landel–Ferry (WLF) equation. Based on the master curves for E′ and E″, one can obtain the relaxation modulus, E( t, T), as a function of time and temperature. The measured thermomechanical and viscoelastic properties of the no-flow underfill material provided crucial material properties for accurately modeling the package stress.

Development of Novel Filler Technology for No-Flow and Wafer Level Underfill Materials

Flip chip technology is one of the fastest growing segments of electronic packaging with growth being driven by the demands such as cost reduction, increase of input/output density, package size reduction and higher operating speed requirements. Unfortunately, flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate, which leads to premature failures of the package. Package reliability can be improved by the application of an underfill. In this paper, we report the development of novel underfill materials utilizing nano-filler technology, which provides a previously unobtainable balance of low CTE and good solder joint formation.

Effect of Underfill Entrapment on the Reliability of Flip-Chip Solder Joint

The application of underfill materials to fill up the room between the chip and substrate is known to substantially improve the thermal fatigue life of flip chip solder joints. Nowadays, no-flow underfill materials are gaining much interest over traditional underfill as the application and curing of this type of underfill can be undertaken before and during the reflow process and thus aiding high volume throughput. However, there is always a potential chance of entrapping no-flow underfill in the solder joints. This work, attempts to find out the extent of underfill entrapment in the solder joints and its reliability effect on the flip chip packages. Some unavoidable underfill entrapments at the edges of the joint between solder bumps and substrate pads are found for certain solder joints whatever bonding conditions are applied. It is interesting to report for the first time that partial underfill entrapment at the edges of the solder joint seems to have no adverse effect on the fatigue lifetime of the samples since most of the first solder joint failure in the no-flow flip chip samples during thermal cycling are not at the site of solder interconnection with underfill entrapment. Our modeling results show good agreement with the experiment that shows underfill entrapment can actually increase the fatigue lifetime of the no-flow flip chip package.

Development of new no-flow underfill materials for both eutectic Sn-Pb solder and a high temperature melting lead-free solder

In recent years, no-flow underfill technology has drawn more attention due to its potential cost-savings advantages over conventional underfill technology, and as a result several no-flow underfill materials have been developed and reported. However, most of these materials are not suitable for lead-free solder, such as Sn/Ag (m.p. 225/spl deg/C), Sn/Ag/Cu (m.p. 217/spl deg/C), applications that usually have higher melting temperatures than the eutectic Sn-Pb solder (m.p. 183/spl deg/C). Due to the increasing environmental concern, the demand for friendly lead-free solders has become an apparent trend. This paper demonstrates a study on two new formulas of no-flow underfill developed for lead-free solders with a melting point around 220/spl deg/C. As compared to the G25, a no-flow underfill material developed in our research group, which uses a solid metal chelate curing catalyst to match the reflow profile of eutectic Sn-Pb solder, these novel formulas employ a liquid curing catalyst thus provides ease in preparation of the no-flow underfill materials. In this study, curing kinetics, glass transition temperature (Tg), thermal expansion coefficient (TCE), storage modulus (E') and loss modulus (E'') of these materials were studied with a differential scanning calorimetry (DSC), a thermo-mechanical analysis (TMA), and a dynamic-mechanical analysis (DMA), respectively. The pot-life in terms of viscosity of these materials was characterized with a stress rheometer. The adhesive strength of the materials on the surface of silicon chips were studied with a die-shear instrument. The influences of fluxing agents on the materials curing kinetics were studied with a DSC. The materials compatibility to the solder penetration and wetting on copper clad during solder reflow was investigated with both eutectic Sn-Pb and 95.9Sn/3.4Ag/0.7Cu solders on copper laminated FR-4 organic boards.

Double-layer no-flow underfill materials and process

The no-flow underfill has been invented and practiced in the industry for a few years. However, due to the interfering of silica fillers with solder joint formation, most no-flow underfills are not filled with silica fillers and hence have a high coefficient of thermal expansion (CTE), which is undesirable for high reliability. In a novel invention, a double-layer no-flow underfill is implemented to the flip-chip process and allows fillers to be incorporated into the no-flow underfill. The effects of bottom layer underfill thickness, bottom layer underfill viscosity, and reflow profile on the solder wetting properties are investigated in a design of experiment (DOE) using quartz chips. It is found that the thickness and viscosity of the bottom layer underfill are essential to the wetting of the solder bumps. Chip scale package (CSP) components are assembled using the double-layer no-flow underfill process. Silica fillers of different sizes and weight percentages are incorporated into the upper layer underfill. With a high viscosity bottom layer underfill, up to 40 wt% fillers can be added into the upper layer underfill and do not interfere with solder joint formation.

Reliability assessment and hygroswelling modeling of FCBGA with no-flow underfill

In the flip-chip ball grid array (FCBGA) assembly process, no-flow underfill has the advantage over traditional capillary-flow underfill on shorter cycle time. Reliability tests are performed on both unmolded and molded FCBGA with three different types of no-flow underfill materials. The JEDEC Level-3 (JL3) moisture preconditioning, followed by reflow and pressure cooker test (PCT) is found to be a critical test for failures of underbump metallization (UBM) opening and underfill/die delamination. In this paper, various types of modeling techniques are applied to analyze the FCBGA-8×8 mm on moisture distribution, hygroswelling behavior, and thermomechanical stress. For moisture diffusion modeling, thermal-moisture analogy is used to calculate the degree of moisture saturation in the multi-material system of FCBGA. The local moisture concentration along the critical interface, e.g. die/underfill, is critical for delamination, because the moisture weakens the interfacial adhesion strength, generates internal vapor pressure during reflow, and induces tensile hygroswelling stress on UBM during PCT. The results of moisture distribution can be used as loading input for the subsequent hygroswelling modeling. The magnitude of hygroswelling stress acting on UBM is found to be greater than the thermal stress induced during reflow, both in tensile mode which may cause the UBM-opening failure. Underfill with lower saturated moisture concentration ( C sat) and coefficient of moisture expansion (CME) are found to induce lower UBM stress and has better reliability results. Molded package generally has higher stress level than unmolded package. Parametric studies are performed to study the effects of no-flow underfill materials, package type (molded vs. unmolded), die thickness, and substrate size on the stresses of UBM during reflow and PCT.

No-flow underfill flip chip assembly––an experimental and modeling analysis

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.

Effect of Moisture on the Interfacial Adhesion of the Underfill/Solder Mask Interface

Moisture poses a significant threat to the reliability of microelectronic assemblies and can be attributed as being the principal cause of many premature package failures. Of particular concern is characterizing the role of moisture with respect to the acceleration of the onset of package delamination. In this paper the effect of moisture on the interfacial fracture toughness of two no-flow underfill materials with a commercially available solder mask coated FR-4 board is experimentally determined. Bilayer specimens with prefabricated interface cracks are used in a four-point bend test to quantify the interfacial fracture toughness. Two groups of test specimens of varying underfill thickness were constructed. The first group was fully dried while the other was moisture preconditioned at 85°C/85%RH for 725 hours. The results of this study show that the interfacial toughness is significantly affected by the presence of moisture.

Assembly of lead-free bumped flip-chip with no-flow underfills

Lead-free solder reflow process has presented challenges to no-flow underfill material and assembly. The currently available no-flow underfill materials are mainly designed for eutectic Sn-Pb solders. This paper presents the assembly of lead-free bumped flip-chip with developed no-flow underfill materials. Epoxy resin/HMPA/metal AcAc/Flux G system is developed as no-flow underfills for Sn/Ag/Cu alloy bumped flip-chips. The solder wetting test is conducted to demonstrate the fluxing capability of the underfills for lead-free solders. A 100% solder joint yield has been achieved using Sn/Ag/Cu bumped flip-chips in a no-flow process. A scanning acoustic microscope is used to observe the underfill voiding. The out-gassing of HMPA at high curing temperatures causes severe voiding inside the package. A differential scanning calorimeter (DSC) used to study the curing degree of the underfill after reflow with or without post-cure. The post-curing profiles indicate that the out-gassing of HMPA would destroy the stoichiometric balance between the epoxy and hardener, and result in a need for high temperature post-cure. The material properties of the underfills are characterized and the influence of underfill out-gassing on the assembly and material properties is investigated. The impact of lead-free reflow on the material design and process conditions of no-flow underfill is discussed.

Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process and no-flow underfill materials

The formation of underfill voids is an area of concern in the low cost, high throughput, or flip chip assembly process. This assembly process involves placement of a flip chip device directly onto the substrate pad site covered with pre-dispensed no-flow underfill. The forced motion of chip placement causes a convex flow front to pass over pad and solder mask-opening features promoting void capture. This paper determines the effects of substrate design on the phenomena of underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing. The substrate design parameters included pad height, solder mask opening height, pad/solder mask opening separation, and pad pitch. The process parameters include chip placement velocity and underfill viscosity. The process robustness is measured in terms of the number of voids created during chip placement, and is further analyzed for the location and any visible modes of void formation. The goal of the work is to determine improved substrate designs to minimize voiding in flip chip processing using no flow underfills.