Nm Of Silicon Nitride Research Articles

Self-organized growth of graphene nanomesh with increased gas sensitivity.

A bottom-up chemical vapor deposition (CVD) process for the growth of graphene nanomesh films is demonstrated. The process relies on silicon nanospheres to block nucleation sites for graphene CVD on copper substrates. These spheres are formed in a self-organized way through silicon diffusion through a 5 μm copper layer on a silicon wafer coated with 400 nm of silicon nitride. The temperature during the growth process disintegrates the Si3N4 layer and silicon atoms diffuse to the copper surface, where they form the nanospheres. After graphene nanomesh growth, the Si nanospheres can be removed by a simple hydrofluoric acid etch, leaving holes in the graphene film. The nanomesh films have been successfully transferred to different substrates, including gas sensor test structures, and verified and characterized by Auger, TEM and SEM measurements. Electrical/gas-exposure measurements show a 2-fold increase in ammonia sensitivity compared to plain graphene sensors. This improvement can be explained by a higher adsorption site density (edge sites). This new method for nanopatterned graphene is scalable, inexpensive and can be carried out in standard semiconductor industry equipment. Furthermore, the substrates are reusable.

Reliability of 100 nm silicon nitride capacitors in an InP HEMT MMIC process

A reliability study has been conducted on capacitors made with 100 nm of silicon nitride, in an InP HEMT MMIC fabrication process. Special wafers were fabricated, containing 1482 200 × 200 μm 2 capacitors each, and these were probed automatically. They were subject to ramped-voltage stress and the breakdown voltages recorded. On a typical wafer the vast majority of the breakdown voltages are between 50 and 90 V. In addition, IV curves were measured on a small number of specimens from 0 V up to breakdown. This was done in two regimes: above 25 V with a conventional setup, and below 25 V with an ultra-low-current measurement system. These were done at 25 and 175 °C above 25 V, and at 25 °C only below 25 V. The data were fitted well with a model for the conductivity, consisting of ohmic conduction at low voltages and Frenkel–Poole conduction at high voltages. Parameters of the fits included thermal activation energies, the voltage acceleration factor in the Frenkel–Poole model, and d eff, the effective thickness of the dielectric at the thinnest point. Analysis invoked the time-dependent dielectric breakdown model, which provides the time to failure as a function of the d eff, while d eff can be found from the ramped-voltage measurements. From the 10 wafers that have been probed so far, the mean of the distribution of failure times (at 1.5 V, 40 °C) is above 5 × 10 7 h, and the distribution becomes insignificant below 2 × 10 6 h. Further, the probability of failure in 10 years at 1.5 V, 40 °C is much less than 1 in 14,600. This indicates that 100 nm silicon nitride capacitors in this technology have good reliability.

Reduction and elimination of proximity effects

The physical processes limiting resolution and causing proximity effects in electron-beam lithography (EBL) are outlined, with the major emphasis on sub-250 nm lithography. A reduction of proximity effects and the enhancement of resolution in the resist can be achieved with a thin intermediate layer (such as 50–300 nm of silicon nitride or silicon dioxide) between the resist and the substrate. This has been observed on a number of substrates (Si, GaAs, W, and InSb) and with two high-resolution e-beam resists. Monte Carlo simulations and experimental results show that secondary electrons play a key role in the understanding of this phenomenon. Furthermore, a large number of fast secondaries (500 eV–3 keV), emitted from substrate–resist interface, enter the resist within a ∼100 nm radius of the primary beam. The thin intermediate layers reduce the number of secondary electrons entering the resist. In contrast, the elimination of proximity effects was observed with very low energy electron beams (≤100 eV) as can be formed by a scanning tunneling microscope (STM), operated in the field emission mode. STM lithography gives a highly localized exposure, which results in very high resist resolution over a wide process latitude. The elements of an implementation of very low voltage EBL are outlined.

Thin silicon nitride films to increase resolution in e-beam lithography

A physical method of reducing feature size and proximity effects in sub-quarter-micrometer e-beam lithography is described. A thin layer (50 to 300 nm) of silicon nitride deposited on a semiconductor substrate, prior to resist deposition, has been found to enhance the resist resolution. The samples were patterned with a 50-keV, 15-nm-diam probe generated by a JEOL JBX-5Dll e-beam lithography system. Point spread function measurements in 60-nm-thick SAL-601 on Si are shown to illustrate the resolution enhancement in the nanolithographic regime (sub-100 nm). The technique has been applied to lithography on 400-nm-thick W films, such as would be used in x-ray mask fabrication. The 200 nm of SAL-601 was spun onto W film samples, which were half-coated with 200 nm of silicon nitride. Identical lithographic patterns were written on each half of the sample. On examination of the samples after postexposure processing and development, reduced feature sizes and proximity effects were seen on the sample half with the silicon nitride intermediary layer. For example, in a field effect transistor (FET) type pattern, with a coded 500-nm gap between the source and drain pads, the gate could only be successfully resolved when the intermediary nitride layer was present. Monte Carlo simulations were performed on a CM-200 connection machine. The results show a large number of fast secondary electrons are generated within a 100-nm radius of the incident electron beam. The implications of fast secondary electrons on resolution in e-beam lithography are discussed. The total number of fast secondary electrons entering the resist is reduced by the silicon nitride layer. Simulations compare the thin-layer technique to a bilayer resist technique, used to improve resolution at larger dimensions.

Changes in surface composition and Fermi level position during thermal desorption of ultraviolet radiation/ozone formed oxides on GaAs

X-ray photoelectron spectroscopy (XPS) has been used to study the native oxide structure and surface Fermi level of GaAs exposed to ultraviolet light (UV)/ozone, as well as to monitor changes that occur during thermal desorption of the surface oxide. The XPS results confirm that the surface oxide consists of a mixture of gallium and arsenic oxide phases which desorb at two different temperature ranges: desorption of arsenic oxide phases and oxygen transfer from arsenic to gallium occur at 250–500 °C; and desorption of gallium oxide phases occurs at 550–600 °C. In addition, we found that the surface Fermi level of GaAs below the UV/ozone formed oxide was always at about 0.8 eV from the valence- band maximum (VBM) for n-type substrates and 0.5 eV for p-type substrates. Similar results were found for wet chemically treated and then air exposed GaAs surfaces. However, the surface Fermi levels of both n- and p-type substrates, during the desorption of arsenic oxide in the temperature range of 250–500 °C, moved further away from VBM by as much as 0.4 eV. When the samples were heated to higher temperatures, the surface Fermi level moved back to midgap even before complete desorption of the gallium oxide phases. Fermi level pinning on samples before and after oxide desorption has also been characterized by in situ deposition of 5 nm of silicon nitride on the sample surface in the XPS system and by monitoring the surface potential of the semiconductor with XPS as a function of charging potential on the dielectric. It was found that surfaces both before and after arsenic oxide desorption were pinned within 0.1 eV with a negative voltage of about 2 V on the thin dielectric.