New Non-volatile Memory Research Articles

The Research of Spark Memory Optimization Based on Non-Volatile Memory

With the advent of the significant data era, more and more data information needs to be processed, bringing tremendous challenges to storage and computing. The spark amount of data is getting larger and larger, and the I/O bottleneck of computing and scheduling from the disk has increasingly become an essential factor restricting performance. The spark came into being and proposed in-memory computing, which significantly improved the computing speed. In addition, the high rate of the memory is easy to lose without power, and the small but expensive feature is also an urgent need to improve. The emergence of new non-volatile memory (NVM) not only brings the characteristics of non-volatile, large capacity, low latency but also brings new opportunities and challenges to the storage system. Therefore, based on the emergence of NVM and the problems to be improved in Spark memory, this paper proposes an NVM-based Spark memory optimization method. Add NVM to the Spark memory system, build a hybrid storage structure of NVM and memory, and make the partition management for NVM storage. What’s more, add some new persistence levels and optimize RDDs and other vital data. In the end, make the related optimization for cache and recovery.

Extending SSD Lifespan with Comprehensive Non-Volatile Memory-Based Write Buffers

New non-volatile memory (NVM) technologies are expected to replace main memory DRAM (dynamic random access memory) in the near future. NAND flash technological breakthroughs have enabled wide adoption of solid state drives (SSDs) in storage systems. However, flash-based SSDs, by nature, cannot avoid low endurance problems because each cell only allows a limited number of erasures. This can give rise to critical SSD reliability issues. Since many SSD write operations eventually cause many SSD erase operations, reducing SSD write traffic plays a crucial role in SSD reliability. This paper proposes two NVM-based buffer cache policies which can work together in different layers to maximally reduce SSD write traffic: a main memory buffer cache design named Hierarchical Adaptive Replacement Cache (H-ARC) and an internal SSD write buffer design named Write Traffic Reduction Buffer (WRB). H-ARC considers four factors (dirty, clean, recency, and frequency) to reduce write traffic and improve cache hit ratios in the host. WRB reduces block erasures and write traffic further inside an SSD by effectively exploiting temporal and spatial localities. These two comprehensive schemes significantly reduce total SSD write traffic at each different layer (i.e., host and SSD) by up to 3x. Consequently, they help extend SSD lifespan without system performance degradation.

Object-oriented recovery for non-volatile memory

New non-volatile memory (NVM) technologies enable direct, durable storage of data in an application's heap. Durable, randomly accessible memory facilitates the construction of applications that do not lose data at system shutdown or power failure. Existing NVM programming frameworks provide mechanisms to consistently capture a running application's state. They do not, however, fully support object-oriented languages or ensure that the persistent heap is consistent with the environment when the application is restarted. In this paper, we propose a new NVM language extension and runtime system that supports object-oriented NVM programming and avoids the pitfalls of prior approaches. At the heart of our technique is object reconstruction, which transparently restores and reconstructs a persistent object's state during program restart. It is implemented in NVMReconstruction, a Clang/LLVM extension and runtime library that provides: (i) transient fields in persistent objects, (ii) support for virtual functions and function pointers, (iii) direct representation of persistent pointers as virtual addresses, and (iv) type-specific reconstruction of a persistent object during program restart. In addition, NVMReconstruction supports updating an application's code, even if this causes objects to expand, by providing object migration. NVMReconstruction also can compact the persistent heap to reduce fragmentation. In experiments, we demonstrate the versatility and usability of object reconstruction and its low runtime performance cost.

TTEC: Data Allocation Optimization for Morphable Scratchpad Memory in Embedded Systems

Scratchpad memory (SPM) is widely utilized in many embedded systems as a software- controlled on-chip memory to replace the traditional cache. New non-volatile memory (NVM) has emerged as a promising candidate to replace SRAM in SPM, due to its significant benefits, such as low-power consumption and high performance. In particular, several representative NVMs, such as PCM, ReRAM, and STT-RAM can build multiple-level cells (MLC) to achieve even higher density. Nevertheless, this triggers off higher energy overhead and longer access latency compared with its single-level cell (SLC) counterpart. To address this issue, this paper first proposes a specific SPM with morphable NVM, in which the memory cell can be dynamically programmed to the MLC mode or SLC mode. Considering the benefits of high-density MLC and low-energy SLC, a simple and novel optimization technique, named theory of thermal expansion and contraction, is presented to minimize the energy consumption and access latency in embedded systems. The basic idea is to dynamically adjust the size configure of SLC/MLC in SPM according to the different workloads of program and allocate the optimal storage medium for each data. Therefore, an integer linear programming formulation is first built to produce an optimal SLC/MLC SPM partition and data allocation. In addition, a corresponding approximation algorithm is proposed to achieve near-optimal results in polynomial time. Finally, the experimental results show that the proposed technique can effectively improve the system performance and reduce the energy consumption.

Write-behind logging

The design of the logging and recovery components of database management systems (DBMSs) has always been influenced by the difference in the performance characteristics of volatile (DRAM) and non-volatile storage devices (HDD/SSDs). The key assumption has been that non-volatile storage is much slower than DRAM and only supports block-oriented read/writes. But the arrival of new non-volatile memory (NVM) storage that is almost as fast as DRAM with fine-grained read/writes invalidates these previous design choices. This paper explores the changes that are required in a DBMS to leverage the unique properties of NVM in systems that still include volatile DRAM. We make the case for a new logging and recovery protocol, called write-behind logging, that enables a DBMS to recover nearly instantaneously from system failures. The key idea is that the DBMS logs what parts of the database have changed rather than how it was changed. Using this method, the DBMS flushes the changes to the database <u>before</u> recording them in the log. Our evaluation shows that this protocol improves a DBMS's transactional throughput by 1.3×, reduces the recovery time by more than two orders of magnitude, and shrinks the storage footprint of the DBMS on NVM by 1.5×. We also demonstrate that our logging protocol is compatible with standard replication schemes.

Preventing STT-RAM Last-Level Caches from Port Obstruction

Many new nonvolatile memory (NVM) technologies have been heavily studied to replace the power-hungry SRAM/DRAM-based memory hierarchy in today's computers. Among various emerging NVM technologies, Spin-Transfer Torque RAM (STT-RAM) has many benefits, such as fast read latency, low leakage power, and high density, making it a promising candidate for last-level caches (LLCs). 1 However, STT-RAM write operation is expensive. In particular, a long STT-RAM cache write operation might obstruct other cache accesses and result in severe performance degradation. Consequently, how to mitigate STT-RAM write overhead is critical to the success of STT-RAM adoption. In this article, we propose an obstruction-aware cache management policy called OAP. OAP monitors cache traffic, detects LLC-obstructive processes, and differentiates the cache accesses from different processes. Our experiment on a four-core architecture with an 8MB STT-RAM L3 cache shows a 14% performance improvement and 64% energy reduction.

Access devices for 3D crosspoint memory

The emergence of new nonvolatile memory (NVM) technologies—such as phase change memory, resistive, and spin-torque-transfer magnetic RAM—has been motivated by exciting applications such as storage class memory, embedded nonvolatile memory, enhanced solid-state disks, and neuromorphic computing. Many of these applications call for such NVM devices to be packed densely in vast “crosspoint” arrays offering many gigabytes if not terabytes of solid-state storage. In such arrays, access to any small subset of the array for accurate reading or low-power writing requires a strong nonlinearity in the IV characteristics, so that the currents passing through the selected devices greatly exceed the residual leakage through the nonselected devices. This nonlinearity can either be included explicitly, by adding a discrete access device at each crosspoint, or implicitly with an NVM device which also exhibits a highly nonlinear IV characteristic. This article reviews progress made toward implementing such access device functionality, focusing on the need to stack such crosspoint arrays vertically above the surface of a silicon wafer for increased effective areal density. The authors start with a brief overview of circuit-level considerations for crosspoint memory arrays, and discuss the role of the access device in minimizing leakage through the many nonselected cells, while delivering the right voltages and currents to the selected cell. The authors then summarize the criteria that an access device must fulfill in order to enable crosspoint memory. The authors review current research on various discrete access device options, ranging from conventional silicon-based semiconductor devices, to oxide semiconductors, threshold switch devices, oxide tunnel barriers, and devices based on mixed-ionic-electronic-conduction. Finally, the authors discuss various approaches for self-selected nonvolatile memories based on Resistive RAM.

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.