Neuromorphic Hardware Platforms Research Articles

Neuromorphic intermediate representation: A unified instruction set for interoperable brain-inspired computing

Spiking neural networks and neuromorphic hardware platforms that simulate neuronal dynamics are getting wide attention and are being applied to many relevant problems using Machine Learning. Despite a well-established mathematical foundation for neural dynamics, there exists numerous software and hardware solutions and stacks whose variability makes it difficult to reproduce findings. Here, we establish a common reference frame for computations in digital neuromorphic systems, titled Neuromorphic Intermediate Representation (NIR). NIR defines a set of computational and composable model primitives as hybrid systems combining continuous-time dynamics and discrete events. By abstracting away assumptions around discretization and hardware constraints, NIR faithfully captures the computational model, while bridging differences between the evaluated implementation and the underlying mathematical formalism. NIR supports an unprecedented number of neuromorphic systems, which we demonstrate by reproducing three spiking neural network models of different complexity across 7 neuromorphic simulators and 4 digital hardware platforms. NIR decouples the development of neuromorphic hardware and software, enabling interoperability between platforms and improving accessibility to multiple neuromorphic technologies. We believe that NIR is a key next step in brain-inspired hardware-software co-evolution, enabling research towards the implementation of energy efficient computational principles of nervous systems. NIR is available at neuroir.org

An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs

Brain-like energy-efficient computing has remained elusive for neuromorphic (NM) circuits and hardware platform implementations despite decades of research. In this work we reveal the opportunity to significantly improve the energy efficiency of digital neuromorphic hardware by introducing NM circuits employing two-dimensional (2D) transition metal dichalcogenide (TMD) layered channel material-based tunnel-field-effect transistors (TFETs). Our novel leaky-integrate-fire (LIF) based digital NM circuit along with its Hebbian learning circuitry operates at a wide range of supply voltages, frequencies, and activity factors, enabling two orders of magnitude higher energy-efficient computing that is difficult to achieve with conventional material and/or device platforms, specifically the silicon-based 7 nm low-standby-power FinFET technology. Our innovative 2D-TFET based NM circuit paves the way toward brain-like energy-efficient computing that can unleash major transformations in future AI and data analytics platforms.

Parametrizing analog multi-compartment neurons with genetic algorithms

Background: Finding appropriate model parameters for multi-compartmental neuron models can be challenging. Parameters such as the leak and axial conductance are not always directly derivable from neuron observations but are crucial for replicating desired observations. The objective of this study is to replicate the attenuation behavior of an excitatory postsynaptic potential (EPSP) traveling along a linear chain of compartments on the analog BrainScaleS-2 neuromorphic hardware platform. Methods: In the present publication we use genetic algorithms to find suitable model parameters. They promise parameterization without domain knowledge of the neuromorphic substrate or underlying neuron model. To validate the results of the genetic algorithms, a comprehensive grid search was conducted. Trial-to-trial variations in the analog system are counteracted utilizing spike-triggered averaging. Results and conclusions: The algorithm successfully replicated the desired EPSP attenuation behavior in both single and multi-objective searches illustrating the applicability of genetic algorithms to parameterize analog neuromorphic hardware.

Canonical circuit computations for computer vision.

Advanced computer vision mechanisms have been inspired by neuroscientific findings. However, with the focus on improving benchmark achievements, technical solutions have been shaped by application and engineering constraints. This includes the training of neural networks which led to the development of feature detectors optimally suited to the application domain. However, the limitations of such approaches motivate the need to identify computational principles, or motifs, in biological vision that can enable further foundational advances in machine vision. We propose to utilize structural and functional principles of neural systems that have been largely overlooked. They potentially provide new inspirations for computer vision mechanisms and models. Recurrent feedforward, lateral, and feedback interactions characterize general principles underlying processing in mammals. We derive a formal specification of core computational motifs that utilize these principles. These are combined to define model mechanisms for visual shape and motion processing. We demonstrate how such a framework can be adopted to run on neuromorphic brain-inspired hardware platforms and can be extended to automatically adapt to environment statistics. We argue that the identified principles and their formalization inspires sophisticated computational mechanisms with improved explanatory scope. These and other elaborated, biologically inspired models can be employed to design computer vision solutions for different tasks and they can be used to advance neural network architectures of learning.

Ion Intercalation Enabled Tunable Frequency Response in Lithium Niobite Memristors

Memristors have emerged as a viable component for developing neuromorphic hardware platforms, which can compete with biological systems in density, accuracy, and energy efficiency. Among contemporary memristive systems, intercalation-driven lithium niobite (LiNbO2) memristors have the advantage of inherent flux-driven large analog conductance tunability ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {R}/{R} &gt;89$ </tex-math></inline-formula> ), a wide resistance range (~10–1E <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7 \Omega $ </tex-math></inline-formula> ) selected via geometry selection, and low-power (~100–150 mV) neuromorphic functionality resembling synaptic weight updates in the synaptic membrane. Emerging neural systems require nonstatic temporal responses to implement temporally diverse architectures, such as recurrent neural networks (RNNs), yet these temporally diverse memristors are rare. There is a gap in understanding of the frequency response of nonvolatile memristors, which is a fundamental characteristic in memristive systems and ultimately dictates the speed of adaptive learning in deployed neural networks and the memory windows available for designers in RNNs. Using both large and small signal characterization methods, these memristors demonstrate up to a decade of span in tunable frequency-dependent response, statically controlled via device geometry and scaling design rules, and dynamically tuned via channel lithium concentration. Thus, the tunable frequency dependence of resistance modulation in LiNbO2 memristors is evaluated, enabling future neural network design rules to be identified for scalable multifunctional memristive systems for neuromorphic computing applications.

A novel un-supervised burst time dependent plasticity learning approach for biologically pattern recognition networks

Bio-inspired computing is an appropriate platform for developing artificial intelligent machines based on the behavioral and functional principles of the brain. Bio-inspired machines have been proven to play a significant role in the development of intelligent systems with spike-based operation being a key feature. However, spikes by themselves do not contain much information and may not cross the synapse and stimulate the post-synaptic neuron while bursts consisting of short trains of high-frequency spikes provide more potent information coding facilities. In this study, a pattern recognition network is proposed that consists of an input layer (adapted from a retinal model), middle layer (bio-inspired spiking neural network with bursting neurons and excitatory and inhibitory AMPA (alpha-amino-3-hydroxy-5-methyl-4-isoxazole-propionic acid) and GABA (Gamma-aminobutyric acid) synapses) and output layer (pyramidal neurons as classifying neurons). For the first time, a novel unsupervised burst-based learning algorithm inspired by spike-time-dependent-plasticity (STDP) is developed, called Burst Time Dependent Plasticity (BTDP). Compared to STDP, BTDP yields a higher performance accuracy and faster convergence rate of spiking pattern recognition networks when classifying EMNIST and CIFAR10 datasets compared to existing spiking networks. The proposed spiking network, trained by the novel unsupervised learning algorithm, is able to compete with advanced deep networks in recognizing complex patterns while being amenable to implementation on neuromorphic hardware platforms.

Design-Technology Co-Optimization for NVM-Based Neuromorphic Processing Elements

An emerging use case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of an ML inference task, making these platforms an attractive solution for embedded ML systems. We present a design-technology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a non-volatile memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality of service of an embedded ML system. At a finer granularity, the latency inside a PE depends on (1) the delay introduced by parasitic components on its current paths, and (2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the quality of service. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing an ML inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of ML inference tasks without incurring high cost-per-bit.

A Light‐Stimulus Flexible Synaptic Transistor Based on Ion‐Gel Side‐Gated Graphene for Neuromorphic Computing

Optogenetic technology is to express the channel proteins that can be act on light for realizing the activity of neurons activated and inhibited. Here, inspired by optogenetics, a flexible side‐gate artificial synaptic transistor based on ion gel and graphene is demonstrated, where the long‐term remembering or forgetting could be activated by the 450 nm light stimulus. Taking advantage of in‐plane‐field tunable carrier transport in graphene and the high ionic motion of ion gels, various synaptic functions under flatting or bending conditions by electric stimuli are successfully mimicked, including inhibition postsynaptic current, excitatory postsynaptic current, and paired‐pulse facilitation. A light‐induced forgetting or remembering is demonstrated by long‐term synaptic plasticity under 20 s and 10 Hz positive or negative gate pulse stimulus in the dark and 4 min recovery with light illumination. Moreover, the light stimulus promotes the associative learning and remembering function, which is demonstrated by Pavlov's dog experiment with electrical pulses and light stimulus. Such light‐assisted learning and memory function on synaptic plasticity can be attributed to the photogenerated electrons trapping effects in our device. The authors’ results provide a feasible strategy for realizing flexible light–electrical‐stimulus synaptic transistors and developing the low‐energy flexible neuromorphic optoelectronic hardware platform.

FPGA-NHAP: A General FPGA-Based Neuromorphic Hardware Acceleration Platform With High Speed and Low Power

Spiking neural network (SNN) can process discrete spikes and offers a high degree of real-time performance and excellent energy efficiency ratio. However, most current neuromorphic hardware platforms lack efficient driven algorithms and only support a single type of neuron model, which has slow speed and poor scalability. This paper proposes a general FPGA-based neuromorphic hardware acceleration platform (FPGA-NHAP), supporting the effective inference and acceleration of SNN network with low power, high speed and good scalability. First, a neuron computing unit is designed to simulate the both LIF and Izhikevich (IZH) neurons with the parallel spike caching and scheduling technique. Second, a novel integrated driven update algorithm is proposed to complete the spike encoding of external data, reducing the waiting time of neuron state update effectively. Third, the proposed platform is implemented using a RISC-V processor and a Xilinx FPGA, simulating 16,384 neurons and 16.8 million synapses with a power consumption of 0.535 W. Finally, two different three-layer SNN networks are deployed on the proposed platform for recognition tasks on the MNIST and Fashion-MNIST datasets, achieving the accuracy of 97.70&#x0025;, 85.14&#x0025; (LIF) and 97.81&#x0025;, 83.16&#x0025; (IZH), frame rates of 208 frame/s, 128 frame/s (LIF) and 206 frame/s, 141 frame/s (IZH), respectively.

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Spiking Neural Networks (SNNs) are an emerging computation model that uses event-driven activation and bio-inspired learning algorithms. SNN-based machine learning programs are typically executed on tile-based neuromorphic hardware platforms, where each tile consists of a computation unit called a crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of the Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine learning programs. Our results demonstrate that DFSynthesizer provides a much tighter performance guarantee compared to current mapping approaches.

Advancements in Algorithms and Neuromorphic Hardware for Spiking Neural Networks.

Artificial neural networks (ANNs) have experienced a rapid advancement for their success in various application domains, including autonomous driving and drone vision. Researchers have been improving the performance efficiency and computational requirement of ANNs inspired by the mechanisms of the biological brain. Spiking neural networks (SNNs) provide a power-efficient and brain-inspired computing paradigm for machine learning applications. However, evaluating large-scale SNNs on classical von Neumann architectures (central processing units/graphics processing units) demands a high amount of power and time. Therefore, hardware designers have developed neuromorphic platforms to execute SNNs in and approach that combines fast processing and low power consumption. Recently, field-programmable gate arrays (FPGAs) have been considered promising candidates for implementing neuromorphic solutions due to their varied advantages, such as higher flexibility, shorter design, and excellent stability. This review aims to describe recent advances in SNNs and the neuromorphic hardware platforms (digital, analog, hybrid, and FPGA based) suitable for their implementation. We present that biological background of SNN learning, such as neuron models and information encoding techniques, followed by a categorization of SNN training. In addition, we describe state-of-the-art SNN simulators. Furthermore, we review and present FPGA-based hardware implementation of SNNs. Finally, we discuss some future directions for research in this field.

Energy-Efficient Respiratory Anomaly Detection in Premature Newborn Infants.

Precise monitoring of respiratory rate in premature newborn infants is essential to initiating medical interventions as required. Wired technologies can be invasive and obtrusive to the patients. We propose a deep-learning-enabled wearable monitoring system for premature newborn infants, where respiratory cessation is predicted using signals that are collected wirelessly from a non-invasive wearable Bellypatch put on the infant’s body. We propose a five-stage design pipeline involving data collection and labeling, feature scaling, deep learning model selection with hyperparameter tuning, model training and validation, and model testing and deployment. The model used is a 1-D convolutional neural network (1DCNN) architecture with one convolution layer, one pooling layer, and three fully-connected layers, achieving 97.15% classification accuracy. To address the energy limitations of wearable processing, several quantization techniques are explored, and their performance and energy consumption are analyzed for the respiratory classification task. Results demonstrate a reduction of energy footprints and model storage overhead with a considerable degradation of the classification accuracy, meaning that quantization and other model compression techniques are not the best solution for respiratory classification problem on wearable devices. To improve accuracy while reducing the energy consumption, we propose a novel spiking neural network (SNN)-based respiratory classification solution, which can be implemented on event-driven neuromorphic hardware platforms. To this end, we propose an approach to convert the analog operations of our baseline trained 1DCNN to their spiking equivalent. We perform a design-space exploration using the parameters of the converted SNN to generate inference solutions having different accuracy and energy footprints. We select a solution that achieves an accuracy of 93.33% with 18× lower energy compared to the baseline 1DCNN model. Additionally, the proposed SNN solution achieves similar accuracy as the quantized model with a 4× lower energy.

A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS

Generally, computer-science-oriented artificial neural networks (ANNs) and neuroscience-oriented spiking neural networks (SNNs) are two main approaches to develop brain-spired non von Neumann computing systems. The goal of exploring complex artificial intelligence (AI) systems demands general neuromorphic hardware platforms compatible with both of them. However, as a result of the obvious differences in their fundamental mathematical expression and coding scheme, many neuromorphic platforms or deep neural network (DNN) accelerators accommodate only one of them. This brief presents a reconfigurable scalable neuromorphic chip based on digital leaky integrate-and-fire (LIF) neuron model targeting low-cost large-scale systems. By unifying ANN and SNN paradigms within a LIF neuron framework with point-to-point (P2P) communication, the chip can accommodate most popular neural networks. The chip adopts distributed on-chip memory architecture with a capacity of 64K neurons and 64M synapses. It achieves a peak throughput of 12.29 GSOP/s at 1.2 V, 192MHz and peak energy efficiency of 2.64 pJ/SOP at 890 mV, 24MHz. The results of implementations of a spike-based spatio-temporal memory model and ternary-weight event-based convolutional neural networks (CNNs) demonstrate outstanding compatibility of the chip.

PageRank Implemented with the MPI Paradigm Running on a Many-Core Neuromorphic Platform

SpiNNaker is a neuromorphic hardware platform, especially designed for the simulation of Spiking Neural Networks (SNNs). To this end, the platform features massively parallel computation and an efficient communication infrastructure based on the transmission of small packets. The effectiveness of SpiNNaker in the parallel execution of the PageRank (PR) algorithm has been tested by the realization of a custom SNN implementation. In this work, we propose a PageRank implementation fully realized with the MPI programming paradigm ported to the SpiNNaker platform. We compare the scalability of the proposed program with the equivalent SNN implementation, and we leverage the characteristics of the PageRank algorithm to benchmark our implementation of MPI on SpiNNaker when faced with massive communication requirements. Experimental results show that the algorithm exhibits favorable scaling for a mid-sized execution context, while highlighting that the performance of MPI-PageRank on SpiNNaker is bounded by memory size and speed limitations on the current version of the hardware.

Optogenetics‐Inspired Neuromorphic Optoelectronic Synaptic Transistors with Optically Modulated Plasticity

AbstractPlasticity modulation, which enables the biological synapses to express rich functionality in a tunable way, is an important technique to comprehensively emulate the synaptic functions for artificial neuromorphic computing systems. However, the reliable modulation on the synaptic plasticity has not been well realized at the device level due to the uncontrollable movement of ions or electrons in solid state electronic materials. Here, inspired by the optogenetics that modifies the synaptic plasticity by optical modulation, the authors propose an optoelectronic synaptic transistor based on MoS2/quantum dots (QDs) mixed‐dimensional heterostructure with optically modulated plasticity. The transmission of neuronal signaling in biological retina has been faithfully emulated under the optical modulation, where the post‐synaptic current is inhibited in the dark and enlarged upon illumination. Moreover, a light‐induced inversion between synaptic potentiation and depression is also demonstrated. Such optical modulation on synaptic plasticity can be attributed to the photo‐gating effect dominating the switching characteristics of the MoS2/QDs heterostructure channel under the stimulation of specific electric signals. The authors’ results provide a feasible strategy to realize functional diversity under the optical modulation for synaptic transistors and promote the development of a neuromorphic optoelectronic hardware platform.

Fan-out and fan-in properties of superconducting neuromorphic circuits

Neuromorphic computing has the potential to further the success of software-based artificial neural networks (ANNs) by designing hardware from a different perspective. Current research in neuromorphic hardware targets dramatic improvements to ANN performance by increasing energy efficiency and speed of operation and even seeks to extend the utility of ANNs by natively adding functionality such as spiking operation. One promising neuromorphic hardware platform is based on superconductive electronics, which has the potential to incorporate all of these advantages at the device level in addition to offering the potential of near lossless communications both within the neuromorphic circuits and between disparate superconductive chips. Here, we explore one of the fundamental brain-inspired architecture components, the fan-in and fan-out as realized in superconductive circuits based on Josephson junctions. From our calculations and WRSPICE simulations, we find that the fan-out should be limited only by junction count and circuit size limitations, and we demonstrate results in simulation at a level of 1-to-10 000, similar to that of the human brain. We find that fan-in has more limitations, but a fan-in level on the order of a few 100-to-1 should be achievable based on current technology. We discuss our findings and the critical parameters that set the limits on fan-in and fan-out in the context of superconductive neuromorphic circuits.

(Invited) Capturing Biological Behavior in Nanomagnetic Artificial Neurons and Synapses for Energy-Efficient Neuromorphic Computing

Modeling computer architecture after the human brain is a promising approach to the ever-increasing demands for real-time processing of massive amounts of data. But, the building blocks of the brain, i.e. neurons and synapses, have more detailed behavior than simply how they are connected, and this behavior is central to their computing efficiency. If we want to capture the energy efficiency of such a neuromorphic architecture, we need devices themselves that can capture the behavior of the biological elements.Magnetic materials and devices have many properties similar to the brain that make them attractive candidates as artificial neurons and synapses. We will present our recent work on designing and modeling three-terminal domain wall-magnetic tunnel junctions (DW-MTJs) that can act as both leaky, integrate, and fire neurons with inherent lateral inhibition [1-2] and as synapses with online learning and spike-timing dependent plasticity behavior [3].The DW-MTJ neuron consists of a perpendicularly magnetized wire containing a single DW and an MTJ on top of the wire, shown in Fig. a. When current is applied to the wire, the DW propagates through spin transfer torque (STT) or spin orbit torque (SOT). The MTJ defines the firing point of the neuron: when the DW moves past the junction, the MTJ resistance switches to generate a spiking current at the MTJ output terminal. We will show results of integration, firing, and inherent leaking of the device. When assembled into a crossbar array as shown in Fig. b, 1-10 digit identification is simulated by measuring which of ten neurons reach the firing point first as shown in Fig. c.Lateral inhibition (LI) is an important function in neuromorphic computing, modeled after the biological neuron behavior that a neuron prevents its less active neighbors in the same layer from firing. In most neuromorphic hardware platforms, LI is implemented with external circuitry, thereby decreasing the energy efficiency and increasing the area overhead of such systems. We show that the DW-MTJ neuron has inherent LI via magnetic interactions. We will show results from modeling current- and field-driven DW motion in adjacent DW-MTJ neurons. Figure d shows that with 90 nm spacing between two 50 nm wide DW-MTJs, the slower device’s DW velocity is drastically reduced from 75 m/s to 20 m/s and a LI of 75% is achieved. The results are explained by current-driven DW velocity characteristics in response to external magnetic fields and are quantified by an analytical model based on the Landau-Lifshitz-Gilbert (LLG) equation. We will show results of arrays of DW-MTJs implementing a soft winner-take-all function and application of the effect to image recognition.We will furthermore present simulation results of the DW-MTJ showing synaptic behavior when the MTJ is made long. By constructing a small circuit around the device we implement spike-timing-dependent plasticity (STDP), where the current flowing through the synapse, which will determine its resistive synaptic weight, is determined by the delay between input and output neurons (Fig. e). We will show that the STDP synapses can process time-dependent input data.The results will be compared with other emerging nonvolatile devices for artificial neural networks. The work presented shows that DW-MTJs can provide a monolithic platform for neuromorphic computing circuits, where both synapses and neurons can be made from the same thin film stack, and motivate further study of magnetic devices for neuromorphic computing.SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525. References N. Hassan, X. Hu, L. Jiang-Wei, W. H. Brigner, O. G. Akinola, F. Garcia-Sanchez, M. Pasquale, C. H. Bennett, J. A. C. Incorvia & J. S. Friedman. Magnetic domain wall neuron with lateral inhibition. J. Appl. Phys. 124, (2018).C. Cui, O. G. Akinola, N. Hassan, H. Christopher, M. J. Marinella, J. S. Friedman & J. A. C. Incorvia. Maximized Lateral Inhibition in Paired Magnetic Domain Wall Racetracks for Neuromorphic Computing. IOP Nanotechnology (2020).O. G. Akinola, X. Hu, C. H. Bennett, M. Marinella, J. S. Friedman & J. A. C. Incorvia. Three-terminal magnetic tunnel junction synapse circuits showing spike-timing-dependent plasticity. J. Phys. D. Appl. Phys. 52, 49LT01 (2019). Figure 1

Maximized lateral inhibition in paired magnetic domain wall racetracks for neuromorphic computing

Lateral inhibition is an important functionality in neuromorphic computing, modeled after the biological neuron behavior that a firing neuron deactivates its neighbors belonging to the same layer and prevents them from firing. In most neuromorphic hardware platforms lateral inhibition is implemented by external circuitry, thereby decreasing the energy efficiency and increasing the area overhead of such systems. Recently, the domain wall—magnetic tunnel junction (DW-MTJ) artificial neuron is demonstrated in modeling to be intrinsically inhibitory. Without peripheral circuitry, lateral inhibition in DW-MTJ neurons results from magnetostatic interaction between neighboring neuron cells. However, the lateral inhibition mechanism in DW-MTJ neurons has not been studied thoroughly, leading to weak inhibition only in very closely-spaced devices. This work approaches these problems by modeling current- and field- driven DW motion in a pair of adjacent DW-MTJ neurons. We maximize the magnitude of lateral inhibition by tuning the magnetic interaction between the neurons. The results are explained by current-driven DW velocity characteristics in response to an external magnetic field and quantified by an analytical model. Dependence of lateral inhibition strength on device parameters is also studied. Finally, lateral inhibition behavior in an array of 1000 DW-MTJ neurons is demonstrated. Our results provide a guideline for the optimization of lateral inhibition implementation in DW-MTJ neurons. With strong lateral inhibition achieved, a path towards competitive learning algorithms such as the winner-take-all are made possible on such neuromorphic devices.

Asynchronous Spiking Neurons, the Natural Key to Exploit Temporal Sparsity

Inference of Deep Neural Networks for stream signal (Video/Audio) processing in edge devices is still challenging. Unlike the most state of the art inference engines which are efficient for static signals, our brain is optimized for real-time dynamic signal processing. We believe one important feature of the brain (asynchronous state-full processing) is the key to its excellence in this domain. In this work, we show how asynchronous processing with state-full neurons allows exploitation of the existing sparsity in natural signals. This paper explains three different types of sparsity and proposes an inference algorithm which exploits all types of sparsities in the execution of already trained networks. Our experiments in three different applications (Handwritten digit recognition, Autonomous Steering and Hand-Gesture recognition) show that this model of inference reduces the number of required operations for sparse input data by a factor of one to two orders of magnitudes. Additionally, due to fully asynchronous processing this type of inference can be run on fully distributed and scalable neuromorphic hardware platforms.

Deep Learning With Spiking Neurons: Opportunities and Challenges.

Spiking neural networks (SNNs) are inspired by information processing in biology, where sparse and asynchronous binary signals are communicated and processed in a massively parallel fashion. SNNs on neuromorphic hardware exhibit favorable properties such as low power consumption, fast inference, and event-driven information processing. This makes them interesting candidates for the efficient implementation of deep neural networks, the method of choice for many machine learning tasks. In this review, we address the opportunities that deep spiking networks offer and investigate in detail the challenges associated with training SNNs in a way that makes them competitive with conventional deep learning, but simultaneously allows for efficient mapping to hardware. A wide range of training methods for SNNs is presented, ranging from the conversion of conventional deep networks into SNNs, constrained training before conversion, spiking variants of backpropagation, and biologically motivated variants of STDP. The goal of our review is to define a categorization of SNN training methods, and summarize their advantages and drawbacks. We further discuss relationships between SNNs and binary networks, which are becoming popular for efficient digital hardware implementation. Neuromorphic hardware platforms have great potential to enable deep spiking networks in real-world applications. We compare the suitability of various neuromorphic systems that have been developed over the past years, and investigate potential use cases. Neuromorphic approaches and conventional machine learning should not be considered simply two solutions to the same classes of problems, instead it is possible to identify and exploit their task-specific advantages. Deep SNNs offer great opportunities to work with new types of event-based sensors, exploit temporal codes and local on-chip learning, and we have so far just scratched the surface of realizing these advantages in practical applications.