Network-on-Chip Research Articles

Fault-tolerant routing for reliable packet transmission in on-chip networks

In deep submicron technology, integrated circuits are susceptible to various factors, leading to increased probabilities of chip failures. The routers within NoC, connecting processor cores, also experience elevated fault rates, thereby impacting normal communication between processors. Therefore, implementing fault-tolerant mechanisms in on-chip networks becomes particularly crucial. In this paper, we propose a fault-tolerant routing scheme to ensure the accurate transmission, injection, and ejection of packets, even in the event of router failures at any node in the NoC. We have enhanced the router architecture by integrating bypass controllers (BCs) to connect east-west and north-south links, and linking these BCs to the local. This modification enables uninterrupted communication between cores. Based on this architecture, we propose a straightforward routing algorithm aimed at minimizing detours and ensuring packet transmission along the shortest path , thus reducing transmission latency. Experimental results demonstrate that our proposed fault-tolerant scheme significantly enhances reliability under scenarios involving multiple faulty routers when compared to existing schemes.

Buffer Association of Network on Chip (NoC) Using Simulated Network

Buffer Association of Network on Chip (NoC) Using Simulated Network

On-chip human lymph node stromal network for evaluating dendritic cell and T-cell trafficking

The lymph node paracortex, also known as the T-cell zone, consists of a network of fibroblastic reticular cells (FRCs) that secrete chemokines to induce T-cell and dendritic cell (DC) trafficking into the paracortex. To model the lymph node paracortex, we utilize multi-channel microfluidic devices to engineer a 3D lymph node stromal network from human cultured FRCs embedded in a collagen I-fibrin hydrogel. In the hydrogel, the FRCs self-assemble into an interconnected network, secrete the extracellular matrix proteins entactin, collagen IV, and fibronectin, as well as express an array of immune cell trafficking chemokines. Although the engineered FRC network did not secrete characteristic CCR7-ligand chemokines (i.e. CCL19 and CCL21), human primary TNF-αmatured monocyte-derived DCs, CD45RA+T-cells, and CD45RA-T-cells migrate toward the lymph node stromal network to a greater extent than toward a blank hydrogel. Furthermore, the FRCs co-recruit DCs and antigen-specific T-cells into the lymph node stromal network. This engineered lymph node stromal network may help evaluate how human DCs and T-cells migrate into the lymph node paracortex via CCR7-independent mechanisms.

Network-on-Chip (NoC) Applications for IoT-Enabled Chip Systems: Latest Designs and Modern Applications

Network-on-Chip (NoC) technology has emerged as a critical innovation in the field of integrated circuit design, addressing the growing demands for efficient, scalable, and high-performance on-chip communication. This review provides a comprehensive examination of NoC, highlighting its architecture, key features, and current applications. NoC leverages a network-based approach, utilizing routers and links to interconnect various components on a chip, thereby overcoming the limitations of traditional System-on-chip (SoC) architectures that rely on shared bus systems. The review underscores NoC’s superior communication efficiency, scalability, and reduced latency, which are essential for modern high-performance computing, multi-core processors, and advanced embedded systems. It also explores NoC’s ability to optimize power consumption through dynamic voltage scaling and power gating, making it a favorable choice for energy-efficient designs. Despite its complexity, NoC’s modularity and adaptability make it suitable for a wide range of applications, from artificial intelligence accelerators to high-performance data centers. In conclusion, NoC stands as a transformative technology that enhances the performance and scalability of integrated circuits, paving the way for more sophisticated and powerful electronic systems. As the demand for higher computational capabilities and efficiency continues to rise, NoC is poised to play an increasingly vital role in the advancement of electronic design and architecture.

F-Bypass: a low-power network-on-chip design utilizing bypass to improve network connectivity

With the development of transistor feature size to nanometer level, static power consumption has gradually become the main factor affecting the overall power consumption of network on chip (NoC). Power gating is an effective technology to reduce static power consumption, but it also brings new challenges, such as BET violation, wake-up latency and network connectivity. Therefore, a power gating method is needed to improve NoC performance and reduce static power consumption. This paper proposes a low-power bypass method, namely Forwarding bypass (F-Bypass). First, F-Bypass adds bypass paths between all input and output ports and the network interface (NI), and connects the pop-up port and injection port in NI through the bypass path. When the router is powered off, F-Bypass performs wake-up-free packet transmission, which reduces the break-even time (BET) violation and cumulative wake-up latency while ensuring network connectivity. Secondly, This paper add the modified VC state table to NI, so that the power-off router can perform normal traffic control. Finally, a new wake-up criterion is proposed, which can effectively avoid the frequent wake-up of power-off routers, and the detailed hardware implementation of F-Bypass is provided.The simulation results under integrated traffic load show that compared with the traditional scheme, the delay of F-Bypass is reduced by 2.2%, the throughput is increased by 13.1%, and the total static power consumption is reduced by 75.2%. Key performance indicators are superior to other solutions, and the increased area cost is moderate.

On-chip photoelectric hybrid convolutional accelerator based on Bragg grating array

We propose an on-chip photoelectric hybrid convolution accelerator based on Bragg grating array. The weight of the convolution kernel can be adjusted by controlling the central wavelengths of the Bragg grating array. We conducted simulation verification of the functionality and scalability of this on-chip photoelectric hybrid convolution accelerator. Subsequently, we constructed a neural network model to conduct handwritten digit classification simulations using this accelerator, achieving a simulation accuracy of 93.99%. Finally, the concept of the proposed on-chip photoelectric hybrid convolution accelerator is successfully verified. Due to the merits of Bragg grating, the proposed scheme paves the way for realizing high-performance on-chip optical neural networks.

Wireless sensor networks protocols, applications, and network-on-chip communications

A wireless sensor network (WSN) is a network consisting of self-governing sensors that are deployed in space and communicate with each other using wireless technology to monitor physical or environmental variables. These networks generally include compact, inexpensive sensor nodes equipped with sensing, processing, and communication functionalities. WSNs are specifically engineered to gather data from their immediate environment, do local data processing, and subsequently communicate pertinent information either to a central hub or to other interconnected nodes within the network. Continuous research in the domain of WSNs is devoted to advancing security concerns, developing novel sensing technologies, and optimizing communication protocols. The advancements in these domains enhance the ongoing development and efficiency of WSNs. The WSNs are very important for getting information from the real world in many situations. WSNs are flexible tools for keeping an eye on and controlling different environments because they have sensor nodes, wireless communication, and distributed processing. WSNs use network-on-chip (NoC) communication architecture to connect sensor nodes. The article explains the introduction to WSN, the background of wireless communication, motivation, ZigBee protocol, and WSN applications.

Proactive deadlock prevention based on traffic classification sub-graphs for triplet-based NoC TriBA-cNoC

Network topology and routing algorithms stand as pivotal decision points that profoundly impact the performance of Network-on-Chip (NoC) systems. As core counts rise, so does the inherent competition for shared resources, spotlighting the critical need for meticulously designed routing algorithms that circumvent deadlocks to ensure optimal network efficiency. This research capitalizes on the Triplet-Base Architecture (TriBA) and its Distributed Minimal Routing Algorithm (DM4T) to overcome the limitations of previous approaches. While DM4T exhibits performance advantages over previous routing algorithms, its deterministic nature and potential for circular dependencies during routing can lead to deadlocks and congestion. Therefore, this work addresses these vulnerabilities while leveraging the performance benefits of TriBA and DM4T. This work introduces a novel approach that merges a proactive deadlock prevention mechanism with Intermediate Adjacent Shortest Path Routing (IASPR). This combination guarantees both deadlock-free and livelock-free routing, ensuring reliable communication within the network. The key to this integration lies in a flow model-based data transfer categorization technique. This technique prevents the formation of circular dependencies. Additionally, it reduces redundant distance calculations during the routing process. By addressing these challenges, the proposed approach achieves improvements in both routing latency and throughput. To rigorously assess the performance of TriBA network topologies under varying configurations, extensive simulations were undertaken. The investigation encompassed both TriBA networks comprising 9 nodes and those with 27 nodes, employing DM4T, IASPR routing algorithms, and the proactive deadlock prevention method. The gem5 simulator, operating under the Garnet 3.0 network model using a standalone protocol for synthetic traffic patterns, was utilized for simulations at high injection rates, spanning diverse synthetic traffic patterns and PARSEC benchmark suite applications. Simulations rigorously quantified the effectiveness of the proposed approach, revealing reductions in average latency 40.17% and 34.05% compared to the lookup table and DM4T, respectively. Additionally, there were notable increases in average throughput of 7.48% and 5.66%.

Unidirectional and hierarchical on-chip interconnected architecture for large-scale hardware spiking neural networks

Spiking Neural Networks (SNNs) exhibit the strong capability to address spatiotemporal dynamic problems. Recent research has explored the hardware SNN systems to solve the spatiotemporal problems in real-time. The Network-on-Chip (NoC) is an effective scheme for building large-scale hardware SNNs. However, for the existing NoC-based hardware SNNs, large area overhead and hardware power are consumed by their interconnections, because of complex topologies and router structures. Therefore, in this work a novel Unidirectional and Hierarchical on-Chip Interconnected Architecture (UHCIA) is proposed to address this problem. The proposed UHCIA mainly combines the novel hybrid topology of unidirectional multiple loops and rings, and uses a deflection router technique. Experimental results show that compared to other works, the UHCIA achieves ∼23.6X of area reduction and ∼6.4X of power reduction, with high system throughput and biological real-time computations.

Performance and energy evaluation of dynamic adaptive deterministic routing algorithm for multicore architectures

Chip Multiprocessors (CMPs) leverage multiple processing units to improve computational speed and efficiency. Routing algorithms in NoC (Network-on-Chip) architectures ensure efficient data communication between these units, addressing challenges such as congestion, latency, and power consumption. This paper delves into an extensive analysis of the performance evaluation concerning the Dynamic Adaptive Deterministic (DyAD) routing for Network-on-Chip (NoC) and Wireless Network-on-Chip (WiNoC) configurations within the framework of a 64-core and 100-core multicore architecture. The evaluation involved a congestion threshold analysis of data transmission latency, the efficiency of network data throughput, and the amount of energy consumed. To substantiate our conclusions, we conducted simulations of the 64-core and 100-core mesh-based NoC and WiNoC architectures under the Video Image Processing System (VIPS) benchmark workload. These simulations were executed utilizing the Noxim simulator, a well-recognized tool acclaimed for its capacity to provide cycle-accurate simulations. Analyzing the simulation outcomes, it becomes evident that the DyAD routing approach for the 64-core and 100-core WiNoC architecture performs better in terms of network performance. It is characterized by enhanced capabilities at higher Packet Injection Rate (PIR) saturation loads, improved network throughput, and minimized latencies. This dominance is evident from its ability to handle heavier workloads and achieve lower delays in the investigated VIPS workload situations, compared to the 64-core and 100-core NoC multicore architecture.

Exploring distance-based wireless transceiver placements for wireless network-on-chip architecture with deterministic routing algorithms

Network-on-chip (NoC) technology is crucial for integrating multiple embed-ded computing cores onto a single chip. Consequently, this has led to the de-velopment of the wireless network-on-chip (WiNoC) concept, seen as a promis-ing strategy to overcome scalability issues in communication systems withinchips for future many-core architectures. This research analyses the impactof wireless transceiver subnet clustering on the hundred-core mesh-structuredWiNoC architecture. The study aims to examine the effects of distance-basedwireless transceiver placements on the transmission delay, network throughput,and energy consumption within a mesh wireless NoC architecture featuring ahundred cores, under specific routing strategies: X-Y, west-first, negative-first,and north-last. This research investigates the impact of positioning radio sub-nets at the farthest, farther, nearest, and closest positions within an architectureequipped with four wireless transceivers. The Noxim simulator was utilised tosimulate the analysed wireless transceiver placements within the hundred-coremesh-structured WiNoC designs, with the objective of validating the results.The architecture with the wireless transceivers positioned at midway proxim-ity (nearer and further) demonstrated the best performance, as evidenced by thelowest latencies for all evaluated deterministic routing algorithms, according tothe simulation outcomes.

Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systems

With the emergence of cutting-edge hardware systems such as cloud computing, edge computing, and on-chip neural network accelerators, how to design advanced memory strategies to substitute the traditional ones for maximizing the potential performance of non-volatile memory (NVM) under the existing hardware conditions, has become an urgent research issue for both academia and industrial communities. It is promising and innovative to improve computer systems in the layer of data exchanging with the emerging advanced semiconductor devices. In the paper, to address the inefficiencies of write-intensive, high power consumption, low hit rate and so on, which exist in hybrid magnetic random access memory cache systems, three novel cache replacement strategies and two cache prefetching strategies are put forward. The proposed triple novel replacement strategies, including historical frequency and time judgments, duplicate data-aware deletion, and dynamic relevance factors computing, can be utilized to compensate for the shortcomings of the traditional least recently used replacement strategy, respectively. In the two novel prefetching strategies, region distribution parameters and Listnet ranking network are imported into the caching process, respectively, to achieve optimized hitting performance. The simulation results demonstrate that the proposed replacement strategies can achieve up to 61.76%, 84.91%, 56.49%, and 53.21% optimization of write count, hit rate, dynamic power, and IPC compared to the conventional one. The proposed prefetching strategy can achieve up to 91.27%, 49.25% hit rate and IPC optimization. Meanwhile, the synthetic evaluation of the replacement and prefetching strategies are elaborated in the paper, including multi-core characteristics, information entropy, interplays and the performance constraints between replacement and prefetching mechanism, which would facilitate more credible ideas for future memory inefficiencies management and strategy design.

A Survey of of Side-Channel Attacks and Mitigation for Processor Interconnects

With advancements in chip technology, the number of cores in modern commercial processors continues to rise, leading to increased complexity in interconnects and on-chip networks. This complexity, however, exposes significant security vulnerabilities, primarily in the form of side-channel and covert-channel exploits. Unlike other microarchitectural side-channel attacks, those leveraging on-chip interconnects utilize unique characteristics, allowing attackers to develop novel methods that can bypass existing effective defenses. In this paper, we present a comprehensive survey of current side-channel and covert-channel attacks based on processor-on-chip interconnects. We categorize these attacks into three types: contention-based, distance-based, and layout-based, according to the specific interconnect characteristics they exploit, and discuss corresponding countermeasures for each. Finally, we provide an outlook on future development trends in processor interconnect side channels. This survey is the first to specifically focus on interconnect-based side channels in processors.

A high-level simulator for Network-on-Chip

This study presents a high-level simulator for Network-on-Chip (NoC), designed for many-core architectures, and integrated with the PlatEMO platform. The motivation for developing this tool arose from the need to evaluate the behavior of application mapping algorithms and the routing, both aspects are essential in the implementation and design of NoC architectures. This analysis underscored the importance of having effective NoC simulators as tools that allow for studying and comparing various network technologies while ensuring a controlled simulation environment. During this investigation and evaluation, some simulators, such as Noxim, NoCTweak, and NoCmap, among others, offered configurable parameters for application traffic, options to synthetically define topology and packet traffic patterns. Additionally, they include mapping options that optimize latency and energy consumption, routing algorithms, technological settings such as the CMOS process, and measurement options for evaluating performance metrics such as throughput and power usage. However, while these simulators meet detailed technical demands, they are mostly restricted to analyzing the low-level elements of the architecture, thus hindering quick and easy under- standing for non-specialists. This insight underscored the challenge in developing a tool that balances detailed analysis with a comprehensive learning perspective, considering the specific restrictions of each simulator analyzed. Experiments demonstrated the proposed simulator efficacy in handling algorithms like GA, PSO, and SA variant, and, surprisingly, revealed limitations of the XY algorithm in Mesh topologies, indicating the need for further investigation to confirm these findings. Future work will expand the simulator functionalities, incorporating a broader range of algorithms and performance metrics, to establish it as an indispensable tool for research and development in NoCs.

NxtSPR: A deadlock-free shortest path routing dedicated to relaying for Triplet-Based many-core Architecture

Deadlock-free routing is a significant challenge in Network-on-Chip (NoC) design as it affects the network’s latency, power consumption, and load balance, impacting the performance of multi-processor systems-on-chip. However, achieving deadlock-free routing will routinely result in expensive overhead as previous solutions either sacrifice performance or power efficiency to proactively avoid deadlocks or impose high hardware complexity to resolve deadlocks when they occur reactively. Utilizing the various characteristics of NoC to implement deadlock-free routing can be significantly more cost-effective with less impact on performance. This paper proposes a relay routing algorithm (NxtSPR) with a shortest path property and a deadlock prevention mechanism based on a synchronized Hamiltonian ring. The proposal is based on an in-depth study of the characteristics of a Triplet-Based many-core Architecture (TriBA) NoC. We establish various important topology-related theories and perform a formal verification (proof-based) for them. By utilizing the critical subgraph and apex of TriBA, NxtSPR can pre-calculate downstream nodes forwarding ports for packets by using a concise judgment strategy. This significantly reduces the computational overhead required for data transmission while optimizing the pipeline design of routers to decrease packet transmission latency and power consumption compared to other TriBA routing algorithms. We group the data transmissions according to the levels of maximum Hamiltonian edges a packet will traverse during its transmission life cycle. Independent data transmissions between groups can avoid mutual interference and resource competition, eliminating potential deadlocks. Gem5 simulation results show that, under the synthetic traffic patterns, compared to the representative (Table) and up-to-date (SPR4T) routing algorithms, NxtSPR achieves a 20.19%, 14.76%, and 5.54%, 4.66% reduction in average packet latency and per-packet power consumption, respectively. Moreover, it has an average of 18.50% and 4.34% improvement in throughput, as compared to them. PARSEC benchmark results show that NxtSPR reduces application runtime by up to a maximum of 22.30% and 12.82% compared to Table and SPR4T, and running the same applications with TriBA results in a maximum runtime reduction of 10.77% compared to 2D-Mesh.

Experimental demonstration of a silicon four-mode (de)multiplexer based on cascaded triple-waveguide couplers

Silicon photonics based on-chip mode-division multiplexing (MDM) is an appealing technology for enhancing the interconnect capacity in both short- and long-haul optical communication. Here, a silicon four-mode (de)multiplexer [(De)MUX] is proposed, optimized, fabricated, and characterized for on-chip MDM systems, based on three cascaded triple-waveguide couplers (TWCs), with coupling lengths below 24.25 µm. A four-mode MDM-link consisting of two back-to-back mode-(De)MUXs was fabricated and measured, yielding a crosstalk of less than −15.0dB over a bandwidth wider than 72.6 nm for four modes. In addition, the TWC based mode (De)MUX demonstrates a 1-dB bandwidth greater than 40 nm, and can be considered as a robust component for multimode on-chip networks.

3D network-on-chip data acquisition system mapping based on reinforcement learning and improved attention mechanism

The three-dimensional Network-on-Chip (NoC) data acquisition system is designed to create a time-interleaved data acquisition system using NoC technology. In the design of NoC application systems, optimizing the mapping algorithm can effectively reduce network communication latency. Aiming at the mapping challenge of a large number of functional IP nodes in 3D NoC data acquisition system, the reinforcement learning and improved attention mechanism mapping algorithm (RA-Map) is proposed. The RA-Map mapping algorithm employs node function encoding and node position encoding to express the properties of an IP node in the task graph preprocessing. The local attention mechanism is used in the mapping network encoder, and the fusion of dynamic key node information is proposed in the decoder. The mapping result evaluation network achieves unsupervised training of the mapping network. These targeted improvements improve the quality of the mapping. Experimental results show that the RA-Map mapping algorithm can effectively model the IP core mapping. Compared with the DPSO algorithm and SA algorithm, the average communication cost of RA-Map mapping algorithm is reduced by 6.5 % and 8.5 %, respectively.

Design of Area Efficient Network-On-Chip Router: A Comprehensive Review

The number of uses for cutting-edge technologies has led to a further growth in a single chip's computational capacity. In this case, several applications want to build on a single chip for computing resources. As a result, connecting the IP cores becomes yet another difficult chore. The many-core System-On-Chips (SoCs) are being replaced by Network-On-Chip (NoC) as an on-chip connectivity option. As a result, the Network on Chip was created as a cutting-edge framework for those networks inside the System on Chip. Modern multiprocessor architectures would benefit more from a NoC architecture as its communication backbone. The most important components of any network structure are its topologies, routing algorithms, and router architectures. NoCs use the routers on each node to route traffic. Circuit complexity, high critical path latency, resource usage, timing, and power efficiency are the primary shortcomings of conventional NoC router architecture. It has been difficult to build a high-performance, low-latency NoC with little area overhead. This paper surveys previous methods and strategies for NoC router topologies and study of general router architecture and its components. Analysis is carried out to understand and work for a low latency, low power consumption, and high performance NoC router design that can be employed with a wide range of FPGA families. In the current work, we are structuring a modified four port router with the goals of low area and high performance operation.

Breaking On-Chip Communication Anonymity using Flow Correlation Attacks

Network-on-Chip (NoC) is widely used to facilitate communication between components in sophisticated System-on-Chip (SoC) designs. Security of the on-chip communication is crucial because exploiting any vulnerability in shared NoC would be a goldmine for an attacker that puts the entire computing infrastructure at risk. We investigate the security strength of existing anonymous routing protocols in NoC architectures, making two pivotal contributions. Firstly, we develop and perform a machine learning (ML)-based flow correlation attack on existing anonymous routing techniques in Network-on-Chip (NoC) systems, revealing that they provide only packet-level anonymity. Secondly, we propose a novel, lightweight anonymous routing protocol featuring outbound traffic tunneling and traffic obfuscation. This protocol is designed to provide robust defense against ML-based flow correlation attacks, ensuring both packet-level and flow-level anonymity. Experimental evaluation using both real and synthetic traffic demonstrates that our proposed attack successfully deanonymizes state-of-the-art anonymous routing in NoC architectures with high accuracy (up to 99%) for diverse traffic patterns. It also reveals that our lightweight anonymous routing protocol can defend against ML-based attacks with minor hardware and performance overhead.

Probability-based mapping approach for an application-aware networks-on-chip architectures

In a digital and automation era, on-chip multi-core architecture plays a vital role in effective communication in the field of very large-scale integrated circuits (VLSI). In this paper, we propose a unique mapping approach in which a probability-based core selection from the application benchmark into the center to eccentric way of placement of cores in the standard network architecture improves the performance of networks-on-chip (NoC). The proposed approach utilizes a structured mapping strategy, in contrast to the random mapping. This characteristic renders the proposed method a robust solution for a diverse range of NoC architectures irrespective of scale. The proposed approach provides better quality of service (QoS) with optimal total communication bandwidth and average hop count. The performance of the proposed mapping approach is validated with various experiments over standard and real-time benchmarks. The investigation results indicate that the total communication cost over real-time NoC benchmarks for the proposed mapping approach offers 43.06%, 22.75%, and 16.69% average improvement over CastNet, NMAP, and mapGtoM respectively. Furthermore, we adopt uniform geometric and shuffled traffic patterns to identify the latency and throughput of the proposed probability-based mapping approach. The investigation results indicate that the proposed mapping approach outperforms existing mapping procedures.