Network-on-Chip Systems Research Articles

Implementation of Dimension Order Routing Algorithm on Reconfigurable Hardware for NoC applications

Inter-processing element communication encounters significant hurdles arising from constraints in power consumption, physical space, and data transfer speed. Storing data packets temporarily during communication uses a lot of the chip's power. Many contemporary network-on-chip (NoC) architectures are heavily resource-intensive due to the extensive use of router buffers. Eliminating these buffers and virtual channels can streamline router design and reduce power consumption. The routing and arbitration strategies implemented within a NoC router are pivotal for optimizing the overall performance of the NoC mesh. The routing algorithm plays a critical role in NoC systems, as it is responsible for balancing traffic load across network channels, even in scenarios of asymmetric traffic distribution. This paper introduces a model for X-Y routing algorithms, specifically tailored for implementation on FPGA platforms utilizing a flexible state diagram. The distinctive contribution of this research lies in its synthesis and optimized realization of the X-Y routing algorithm on FPGAs, providing Network-on-Chip (NoC) designers with a robust framework for developing efficient routers tailored to their FPGA architectures.

IWO-IGA—A Hybrid Whale Optimization Algorithm Featuring Improved Genetic Characteristics for Mapping Real-Time Applications onto 2D Network on Chip

Network on Chip (NoC) has emerged as a potential substitute for the communication model in modern computer systems with extensive integration. Among the numerous design challenges, application mapping on the NoC system poses one of the most complex and demanding optimization problems. In this research, we propose a hybrid improved whale optimization algorithm with enhanced genetic properties (IWOA-IGA) to optimally map real-time applications onto the 2D NoC Platform. The IWOA-IGA is a novel approach combining an improved whale optimization algorithm with the ability of a refined genetic algorithm to optimally map application tasks. A comprehensive comparison is performed between the proposed method and other state-of-the-art algorithms through rigorous analysis. The evaluation consists of real-time applications, benchmarks, and a collection of arbitrarily scaled and procedurally generated large-task graphs. The proposed IWOA-IGA indicates an average improvement in power reduction, improved energy consumption, and latency over state-of-the-art algorithms. Performance based on the Convergence Factor, which assesses the algorithm’s efficiency in achieving better convergence after running for a specific number of iterations over other efficiently developed techniques, is introduced in this research work. These results demonstrate the algorithm’s superior convergence performance when applied to real-world and synthetic task graphs. Our research findings spotlight the superior performance of hybrid improved whale optimization integrated with enhanced GA features, emphasizing its potential for application mapping in NoC-based systems.

Defense Against On-Chip Trojans Enabling Traffic Analysis Attacks Based on Machine Learning and Data Augmentation

Modern computing systems involve huge data exchange across various sections of the processing system. To facilitate this, Network-on-Chip (NoC) serve as a crucial infrastructure that connect the processing cores to memory, peripherals, etc. The system could be put at great risk should the NoC system become compromised. The NoCs are used in multi/many-core processors; this domain is experiencing increased threats because of Hardware Trojan (HT) embedded in the multi core processing systems due to the presence of third-party entities in the system-on-chip (SoC) design pipeline. Protecting user and system level privacy becomes important in such multi core systems to enable trust. By embedding a hardware Trojan (HT) in a NoC, the adversary can snoop on important insights regarding the applications executing on the system or the user profile information. An attack of such calibre can compromise privacy thereby enabling more advanced attack on the entire system. This work demonstrates the capability of a traffic analysis attack when a few HTs are embedded in the NoC switches of a multi/many-core processor. The attack is capable of exposing sensitive information to an external malicious attacker who can then analyze the payload data with sophisticated machine learning (ML) techniques to infer the applications executing on the system. We also evaluate the performance of a generative adversarial network (GAN) strengthened attacker model that offers more robustness for data paucity scenarios. We propose a Simulated Annealing-based randomized routing algorithm based defense for NoCs thus thwarting the attack. The results demonstrate that the proposed randomized routing algorithm could reduce the accuracy of identifying user profiles by the attacker from >98% to <15% in multi/many-core systems.

Adaptive Machine Learning-Based Proactive Thermal Management for NoC Systems

Because of the high-complex interconnection in contemporary multicore systems, the network-on-chip (NoC) technology has been proven as an efficient way to solve the communication problem in multicore systems. However, the thermal problem becomes the main design challenge in the current NoC systems due to the high-diverse workload distribution and large power density. Therefore, proactive dynamic thermal management (PDTM) is employed as an efficient way to control the system temperature. Based on the predicted temperature information, the PDTM can control the system temperature in advance to reduce the performance impact during the temperature control period. However, conventional temperature prediction models are usually built based on specific physical parameters, which are usually temperature-sensitive. Consequently, the current temperature prediction models still result in significant temperature prediction errors. To solve this problem, a novel adaptive machine learning (ML)-based PDTM is proposed in this work. The adaptive ML-based PDTM first uses an adaptive single layer perceptron (ASLP), which is composed of a single-neuron operation and a least mean square (LMS) adaptive filter technology, to precisely predict the future temperature. Afterward, the proposed adaptive reinforcement learning (RL) is used to find the proper throttling ratio to control the system temperature. In this way, the proposed adaptive ML-based PDTM can adapt to the hyperplane of the temperature behavior of the NoC system and provide a proper temperature control strategy at runtime. Compared with related works, the proposed approach reduces average temperature prediction error by 0.2%–78.0% and improves the system performance by 2.4%–43.0% with smaller hardware overhead.

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

We propose a network-on-chip (NoC)-based whole system design, whose communication architecture is compatible with the advanced microcontroller bus architecture advanced extensible interface 4 (AXI4) protocol and supports high-performance multiple quality-of-service (QoS) schemes. In our system, the network interface (NI) between the NoC and the master/slave node is proposed to make the NoC architecture independent from the AXI4 protocol via message format conversion between the AXI4 signal format and the packet format, offering high flexibility to the NoC design. Besides, a QoS inheritance mechanism is applied in the slave-side NI to support QoS during packets’ round-trip transfer in the NoC. The NoC system contains time-division multiplexing (TDM) and virtual channel (VC) subnetworks to apply multiple QoS schemes to AXI4 signals with different QoS tags, and the NI is responsible for signals distribution between two subnetworks. Besides, a traffic converter is proposed in each NI to balance the traffic between the two subnetworks when necessary. The experimental results show that our proposed architecture ensures a high-throughput and low-latency NoC system. By applying the traffic converter, the packet latency can be improved.

An Efficient Algorithm for Mapping Deep Learning Applications on the NoC Architecture

Network-on-chip (NoC) is replacing the existing on-chip communication mechanism in the latest, very-large-scale integration (VLSI) systems because of their fault tolerant design. However, in addition to the design challenges, NoC systems require a mechanism for proper application mapping in order to produce maximum benefits in terms of application-level latency, platform energy consumption, and system throughput. Similarly, the neural-network (NN)-based artificial intelligence (AI) techniques for deep learning are gaining particular interest. These applications can be executed on a cloud-based system, but some of these applications have to be executed on private cloud to integrate the data privacy. Furthermore, the public cloud systems can also be made from these NoC platforms to have better application performance. Therefore, there is a need to optimally map these applications on existing NoC-based architectures. If the application is not properly mapped, then it can create a performance hazard that may lead to delay in calculations, increase in energy consumption, and decrease in the platform lifetime. Hence, the real-time applications requiring AI services can implement these algorithms in NoC-based architectures with better real-time performance. In this article, we propose a multilevel mapping of deep learning AI applications on the NoC architectures and show its results for the energy consumption, task distribution profile, latency, and throughput. The simulation is conducted using the OCTAVE, and the simulation results show that the performance of the proposed mapping technique is better than the direct mapping techniques.

An Evaluation of Routing Algorithms in Traffic Engineering and Quality of Service Provision of Network on Chips

Nowadays the number of cores that are integrated into NoC (Network on Chip) systems is steadily increasing, and real application traffic, running in such multi-core environments requires more and more bandwidth. In that sense, NoC architectures should be properly designed so as to provide efficient traffic engineering, as well as QoS support. Routing algorithm choice in conjunction with other parameters, such as network size and topology, traffic features (time and spatial distribution), as well as packet injection rate, packet size, and buffering capability, are all equivalently critical for designing a robust NoC architecture, on the grounds of traffic engineering and QoS provision. In this paper, a thorough numerical investigation is achieved by taking into consideration the criticality of selecting the proper routing algorithm, in conjunction with all the other aforementioned parameters. This is done via implementation of four routing evaluation traffic scenarios varying each parameter either individually, or as a set, thus exhausting all possible combinations, and making compact decisions on proper routing algorithm selection in NoC architectures. It has been shown that the simplicity of a deterministic routing algorithm such as XY, seems to be a reasonable choice, not only for random traffic patterns but also for non-uniform distributed traffic patterns, in terms of delay and throughput for 2D mesh NoC systems.

ParRouting: An Efficient Area Partition-Based Congestion-Aware Routing Algorithm for NoCs.

Routing algorithms is a key factor that determines the performance of NoC (Networks-on-Chip) systems. Regional congestion awareness routing algorithms have shown great potential in improving the performance of NoC. However, it incurs a significant queuing latency when practitioners use existing regional congestion awareness routing algorithms to make routing decisions, thus degrading the performance of NoC. In this paper, we propose an efficient area partition-based congestion-aware routing algorithm, ParRouting, which aims at increasing the throughput and reducing the latency for NoC systems. First, ParRouting partitions the network into two areas (i.e., edge area and central area.) based on node priorities. Then, for the edge area, ParRouting selects the output node based on different priorities for higher throughput; for the central area, ParRouting selects the node in the low congestion direction as the output node for lower queuing latency. Our experimental results indicate that ParRouting achieves a 53.4% reduction in packet average latency over SPLASH -2 ocean application and improves the saturated throughput by up to 38.81% over a synthetic traffic pattern for an NoC system, compared to existing routing algorithms.

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the high-performance constraints of composite embedded applications is on the rise. This leads to the realization of efficient mapping approaches for such complex applications. The significance of efficient application mapping approaches has increased ever since the embedded applications have become more complex and performance-oriented. This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation. These approaches target to improve the performance of the whole system by optimizing communication cost, energy, power consumption, and latency. Apart from the categorization of the discussed approaches, comparison of communication cost, power, energy, and latency of the NoC system carried out on real applications like VOPD and MPEG4. Moreover, the best technique identified in each category based on the evaluation of performance results.

On Runtime Communication and Thermal-Aware Application Mapping and Defragmentation in 3D NoC Systems

Many-core systems connected by 3D Networks-on-Chip (NoC) are emerging as a promising computation engine for systems like cloud computing servers, big data systems, etc . Mapping applications at runtime to 3D NoCs is the key to maintain high throughput of the overall chip under a thermal/power constraint. However, the goals of optimizing both the communication latency and chip peak temperature are contradicting due to several reasons. First, exploiting the vertical TSV links can accelerate communications, while low peak temperature prefers that the tasks to be mapped closer to the heat sink, instead of using the vertical links. Second, mapping tasks in close proximity can reduce communication latency, but at the cost of poor heat dissipation. To address these issues, in this paper, we propose an efficient runtime mapping algorithm to reduce both communication latency and overall application running time under thermal constraint. In essence, this algorithm first selects a 3D cuboid core region of a specific shape for each incoming application by setting the region's number of occupied vertical layers and its distance to the heat sink, in order to optimize its communication performance and peak temperature. Next, the exact locations of the core regions in the chip are determined, followed by a task-to-core mapping. A defragmentation algorithm is also proposed to keep free core regions contiguous. The experimental results have confirmed that, compared to two recently proposed runtime mapping algorithms, our proposed approach can reduce the total running time by up to 48% and communication cost by up to 44%, with a low runtime overhead.

A Proficient Performance Scrutiny of King Mesh Topology based on the Routing Algorithms

Network on Chip (NoC), is an associate degree approach to construct the interaction between subsystems. The number of cores in a System on Chip (SoC) increases gradually in the pre-decades and affect the system performance. The scalability of SoC is improved by NoC architectures where topology contains an important impact on the performance and cost of the network. Mesh, Torus is some of the topologies used in NoC system design. King mesh topology is the concept introduced to improve the performance of the NoC system. King topology introduces some new advancement in the performance of mesh and torus topology. The king mesh topology provides number of advantages such as reduced execution time in parallel processing applications. In king mesh topology the transmission latency of long distance traffic is high. The proposed XY routing and Weight based Path Selection (WPS) routing techniques increases the speed of the system, reduce the area utilization and power consumption and reduce the number of hop counts by finding the shortest path.

A Communication Probability-Based Mapping Algorithm for Mesh-Based Network-on-Chip Systems

Network-on-chip (NoC) mapping algorithms significantly affect NoC system performance in terms of communication cost and energy consumption. For a specific application represented by a task graph, this paper proposes an energy-efficient mapping algorithm that searches for the mapping decision with best communication locality and therefore lowest energy consumption. To this end, we formulate the concerned mapping problem as an optimization model, and propose an effective meta-heuristic algorithm to solve the formulated optimization model. During the mapping procedure, we employ a simulation-free, communication probability-based energy model to evaluate the quality of each candidate mapping. By iteratively updating the best explored mapping decision using a meta-heuristic search strategy, the mapping procedure can eventually identify an mapping decision with optimal energy efficiency in the search space. The proposed mapping algorithm has been verified on NoC systems of different sizes using a variety of benchmark applications. Simulation results demonstrate that the mapping decision produced by this algorithm achieves an up to 23% energy reduction compared with the traditional round-robin strategy.

An Efficient Algorithm for Mapping Real Time Embedded Applications on NoC Architecture

Network-on-chip (NoC) has appeared to be an impending substitute for the communication paradigm in modern very large scale integration embedded systems. Apart from many design challenges, application mapping on the NoC system is one of the most intractable and challenging optimization problems. In this paper, we propose a hybrid, branch & bound (BB)-based exact mapping (BEMAP) algorithm, for mapping real-time embedded applications on the NoC architecture. The BEMAP optimizes the latency and throughput of the NoC system and minimizes power consumption under the bandwidth constraint. This method utilizes the modular exact and systematic search optimization techniques to obtain a multi-objective optimized solution to the mapping problem of the NoC designs. The proposed algorithm exploits the state-of-the-art BB algorithm, in order to obtain optimized results against its competitors. Experimental results under the benchmarks of several real-time embedded applications show that the proposed algorithm achieves up to 19.93% savings in power consumption and 61.10% improvement in network latency for two dimension mesh and torus topologies.

Bandwidth-Constrained Multi-Objective Segmented Brute-Force Algorithm for Efficient Mapping of Embedded Applications on NoC Architecture

Network-on-chip (NoC) is an emerging alternative to address the communication problem in embedded system-on-chip designs. One of the key and major issues is the optimized mapping of the embedded applications on the underlined NoC platform. In this paper, we propose the bandwidth-constrained multi-objective segmented brute-force mapping (SBMAP) algorithm, which minimizes the communication energy consumption and reduces the computational complexity of the NoC designs. The algorithm generates efficient mapping of the embedded applications on the processing elements of the NoC system by segregating the application into multiple segments. It utilizes the property of modular systematic search, which produces high-performance results with optimized simulation time. We compared the SBMAP algorithm with the state-of-the-art mapping techniques, such as branch and bound (BB), near-optimal mapping (NMAP), and random mapping algorithms for mapping real-world application workloads. The experimental results validated the efficiency of the proposed algorithm against its competitors for most of the performance parameters of the NoC designs. The improvement in energy consumption of the SBMAP algorithm is up to 53% for 2-D mesh and 62% for torus topology as compared with the NMAP, BB, and random algorithms for video object plane decoder, picture in picture, Wi-Fi receiver, and multimedia system real-time application benchmarks.

A power-optimized, area-efficient implementation of Connection-Then-Credit NoC physical layer

This paper discusses the implementation details of a complete NoC physical layer, basically, the Networks-on-Chip (NoC) routers, links and interfaces. A cycle-accurate RTL design details of complete NoC using a mesh-topology is presented with a special attention to the design of the NoC interface. The proposed implementation provides a complete end-to-end solution for an NoC system in a modular architecture, along with its advanced verification environment, to serve as a development and test platform for future NoC research. The paper also analyzes the performance of the Connection-Then-Credit (CTC) protocol and compares it to the conventional Credit-based (CB) protocol using standard traffic patterns, as well as its post-synthesis implementation results using TSMC 40nm low-power CMOS technology. Through the addition of a low-power controller to the CTC-based NoC interfaces, our experimental results show a significant efficiency improvement in terms of power-savings, latency and area overhead. The CTC implementation achieved 21.46% saving in power consumption for the VOPD benchmark. In terms of gate-count, the CTC implementation of VOPD, MPEG, and MWD benchmarks achieved 14.40%, 34.05%, and 7.44% less gate counts, respectively.

Action-Level Real-Time Network-on-Chip Modeling

To simulate time-constrained operations and scheduling for Network-on-Chip (NoC) systems, we introduce a new set of component specifications at flit level grounded in Action-Level Real-Time DEVS formalism. These models capture the dynamics of NoC systems through action-based behavior under strict execution time intervals. These DEVS-based models are well-suited for development and simulation of asynchronous NoC architectures. This is achieved by extending the DEVS-Suite simulator to support real-time executions of ALRT-DEVS models. Representative simulation models capturing structure and behavior of prototypical Mesh NoC systems are developed. A set of experiments are designed, implemented, executed, and analyzed to show the kind of real-time simulation capabilities that can be achieved for Network-on-Chip systems.

Genetic algorithm for task mapping in embedded systems on a hierarchical architecture based on wireless network on chip WiNoC

Los sistemas de red en chip (NoC) fueron desarrollados originalmente para proporcionar un alto rendimiento, mediante la disponibilidad de varias unidades de procesamiento, conectadas a través de una red cableada dentro del circuito integrado. Wireless NoC (WiNoC o WNoC) son una evolución natural de los sistemas NoC, que integran una comunicación jerárquica dentro del chip para mejorar la escalabilidad. El mapeo de tareas en los sistemas WNoC representa un proceso desafiante, que a menudo implica varios objetivos de optimización, como potencia, rendimiento, productividad, uso de recursos y métricas de red. Este artículo describe un algoritmo genético basado en un enfoque para encontrar soluciones óptimas de asignación de tareas en tiempo de diseño, para sistemas embebidos que trabajan sobre un WiNoC. Los objetivos de optimización fueron: Aceleración, Consumo de Energía y Ancho de Banda. La red de destino utilizada para la simulación puede ser vista como un WiNoC jerárquica de dos niveles. El primer nivel corresponde a un conjunto de subredes que están conectadas por cables y son de tipo malla. El segundo nivel corresponde a una topología en estrella de enlaces inalámbricos, que conectan las subredes de primer nivel. El algoritmo propuesto muestra un buen desempeño en relación con los objetivos de optimización y la WiNoC heterogéneo simulada.

Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems

Network-on-Chip (NoC) is the regular and scalable design architecture for chip multiprocessor (CMP) systems. With the increasing number of cores and the scaling of network in deep submicron (DSM) technology, the NoC systems become subject to manufacturing defects and have low production yield. Due to the fault issues, the reduction in the number of available routing paths for packet delivery may cause severe traffic congestion and even to a system crash. Therefore, the fault-tolerant routing algorithm is desired to maintain the correctness of system functionality. To overcome fault problems, conventional fault-tolerant routing algorithms employ fault information and buffer occupancy information of the local regions. However, the information only provides a limited view of traffic in the network, which still results in heavy traffic congestion. To achieve fault-resilient packet delivery and traffic balancing, this work proposes a Path-Diversity-Aware Fault-Tolerant Routing ( PDA-FTR ) algorithm, which simultaneously considers path diversity information and buffer information. Compared with other fault-tolerant routing algorithms, the proposed work can improve average saturation throughput by 175 percent with only 8.9 percent average area overhead and 7.1 percent average power overhead.

A low-overhead soft–hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems

The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution to handle the strict communication requirements between the increasingly large number of cores on a single chip. However, NoC systems are exposed to the aggressive scaling down of transistors, low operating voltages, and high integration and power densities, making them vulnerable to permanent (hard) faults and transient (soft) errors. A hard fault in a NoC can lead to external blocking, causing congestion across the whole network. A soft error is more challenging because of its silent data corruption, which leads to a large area of erroneous data due to error propagation, packet re-transmission, and deadlock. In this paper, we present the architecture and design of a comprehensive soft error and hard fault-tolerant 3D-NoC system, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO). With the aid of efficient mechanisms and algorithms, 3D-FETO is capable of detecting and recovering from soft errors which occur in the routing pipeline stages and leverages reconfigurable components to handle permanent faults in links, input buffers, and crossbars. In-depth evaluation results show that the 3D-FETO system is able to work around different kinds of hard faults and soft errors, ensuring graceful performance degradation, while minimizing additional hardware complexity and remaining power efficient.

A Fault-Tolerant Deflection Routing for Network-on-Chip

Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.