FPGA Network Research Articles

Time error accumulation in a hierarchical time and clock distribution network with deterministic optical links

Accurate clock and time distribution is a key requirement for self-triggered streaming data acquisition in the CBM experiment. This distribution is handled by the Timing and Fast Control (TFC) system by clock forwarding and broadcasting the common time over latency-deterministic optical links in a hierarchical FPGA network. The point-to-point optical connections are served by the latency-optimized GBT-FPGA core, which has been developed at CERN. In the presented work, the performance of GBT-FPGA links for time and clock distribution in a scaled TFC system with multiple hops and endpoints has been investigated.

Binary Neural Networks in FPGAs: Architectures, Tool Flows and Hardware Comparisons.

Binary neural networks (BNNs) are variations of artificial/deep neural network (ANN/DNN) architectures that constrain the real values of weights to the binary set of numbers {-1,1}. By using binary values, BNNs can convert matrix multiplications into bitwise operations, which accelerates both training and inference and reduces hardware complexity and model sizes for implementation. Compared to traditional deep learning architectures, BNNs are a good choice for implementation in resource-constrained devices like FPGAs and ASICs. However, BNNs have the disadvantage of reduced performance and accuracy because of the tradeoff due to binarization. Over the years, this has attracted the attention of the research community to overcome the performance gap of BNNs, and several architectures have been proposed. In this paper, we provide a comprehensive review of BNNs for implementation in FPGA hardware. The survey covers different aspects, such as BNN architectures and variants, design and tool flows for FPGAs, and various applications for BNNs. The final part of the paper gives some benchmark works and design tools for implementing BNNs in FPGAs based on established datasets used by the research community.

Effective switchless inter-FPGA memory networks

FPGA network bandwidth increases to 400 Gbps or higher by high-density optical integration, e.g., Co-Packaged Optics (CPO) and onboard Si-photonics transceivers. This study presents its lightweight switchless network architecture by exploiting an indirect path, consisting of up to k one-hop paths for a diameter-k network topology. It integrates interconnection network and memory channels into a lightweight memory-to-memory inter-FPGA network. It has a uni-directional network topology for connecting the largest number of FPGAs. A newly introduced indirect flow control enables lossless uni-directional networks. We present multi-path point-to-point communications, multi-port message-combine collective communications, and efficient WDM (Wavelength Division Multiplexing) cabling method for the uni-directional networks. We implement and evaluate the uni-directional switchless network on an FPGA cluster consisting of six custom Stratix10 MX2100 FPGA cards connected with a 16-wavelength Arrayed Waveguide Grating (AWG) router. Simulation results show that the multi-port message-combine collective communication achieves 7× faster than conventional communication with 272 FPGAs. Effective WDM cabling using 16 wavelengths decreases the number of cables by 88% compared with parallel optical cabling for 272 FPGAs.

Implementation of convolutional NEURAL network in FPGA for image recognition

Implementation of convolutional NEURAL network in FPGA for image recognition

Highly-Parallel Hardwired Deep Convolutional Neural Network for 1-ms Dual-Hand Tracking

1-ms vision systems represent an extreme case of temporal development in video sensing techniques. Moreover, a 1-ms dual-hand tracking system leverages the dexterous functionality of hands and thus serves as a seamless and intuitive interface for Human-Computer Interaction. Deep CNN is promising for high tracking robustness, however, neither GPU-based nor FPGA-based implementation addresses the tracking task with ultra-high-speed. This paper proposes: (a) A paradigm to directly map a deep CNN as a hardwired circuit, so the entire network runs in parallel and high processing speed is obtained. The network is exempted from memory access since all intermediate neural values are implicitly represented in hardware states. And condensed binarization is used to reduce resource utilization; (b) Hardware design of the hardwired network on FPGA, inside which kernel-adapted convolutional trees are devised to maximize the parallelism. The speed bottleneck of the network is therefore removed by implementing convolutional layers as fine-grained pipelines with unified components; (c) FPGA-GPU hetero complementation, which utilizes an auxiliary GPU network to compensate for accuracy of the FPGA network without affecting its speed. The quick primary results on FPGA are intermittently refined using delayed but accurate hints from GPU. Implementation results show that the proposed method reaches 973fps and consumes merely 1.30ms to process on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$640\times 480$ </tex-math></inline-formula> images, while the accuracy is only 4.7% lower compared with the general method on test sequences. Video demonstrations are available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://wcms.waseda.jp/em/5f9d020f136e7</uri> .

Implementation of convolutional Neural network in FPGA for image Recognition

Implementation of convolutional Neural network in FPGA for image Recognition

Optimization of the Convolution Operation to Accelerate Deep Neural Networks in FPGA

In recent years, machine learning algorithms related to images have been widely utilized by Convolution Neural Networks (CNN), and it has a high accuracy for recognition of an image. As CNN contains large number of computations, hardware accelerator like Field Programmable Gate Array is employed. Quite 90 % of operations during a CNN involves convolution. The objective of this work is to scale back the computation time to increase the peak, width and the pixel intensity levels in the input image. The execution time of a image processing program is mostly spent on loops. Loop optimization is a process of accelerating speed and reducing the overheads related to loops. It plays a crucial role in improving performance and making effective use of multiprocessing capabilities. Loop unrolling is one of the loop optimization techniques. In our work CNN with four levels of loop unrolling is used. Due to this delay is reduced compared with conventional Xilinix. With the assistance of strides and padding the 40 % of computation time has been reduced and is verified in MATLAB.

Robust Convolutional Neural Networks in SRAM-based FPGAs: a Case Study in Image Classification

This work discusses the main aspects of vulnerability and degradation of accuracy of an image classification engine implemented into SRAM-based FPGAs under faults. The image classification engine is an all-convolutional neural-network (CNN) trained with a dataset of traffic sign recognition benchmark. The Caffe and Ristretto frameworks were used for CNN training and fine-tuning while the ZynqNet inference engine was adopted as hardware implementation on a Xilinx 28 nm SRAM-based FPGA. The CNN under test was generated using an evolutive approach based on genetic algorithm. The methodologies for qualifying this CNN under faults is presented and both heavy-ions accelerated irradiation and emulated fault injection were performed. To cross validate results from radiation and fault injection, different implementations of the same CNN were tested using reduced arithmetic precision and protection of user data by Hamming codes, in combination with configuration memory healing by the scrubbing mechanism available in Xilinx FPGA. Some of these alternative implementations increased significantly the mission time of the CNN, when compared to the original ZynqNet operating on 32 bits floating point number, and the experiment suggests areas for further improvements on the fault injection methodology in use.

RETRACTED: Computer simulation of urban garden landscape design based on FPGA and neural network

Digital Landscape is a combination of the system and the computer software and hardware system of a high simulation model. The author analyzes the application of computer simulation in landscape design and value analysis of a city garden. In the computer-aided design, the importance of digitizing information in the landscape design process, mainly human and the interaction of computer, is reflected in the digital model's creation and multimedia performance, becoming more and more evident. To form a two-dimensional or three-dimensional spatial data, to realize real-time, statistical Analysis, using the human living environment, multi-dimensional, efficient, and humane, and environmental landscape plan to more rational and practical, used the computer simulation techniques. Effective use of urban rainwater, to reduce the flooding of urban areas, it is possible to alleviate the water crisis, the organic combination of rainwater can be used in the course of the construction of the urban landscape as well as make-up landscape, visual beautification has optimized the ecosystem, and from many rainwater utilization functions; These functions in landscape design, rainwater garden, It can be realized the rooftop garden, and the city's green. The construction and sustainable economy and the promotion of the ecological park's social development will positively sign. Suitable for rainwater regulation, water (recovery) is stored—Computer-Aided Design (CAD) green space. Technical measures save of suggestions for practical application of the square: innovation and new of space design, new artificial wetland system, and garden rainwater in the application of the regulation (population) storage system design of the water-saving of these to the sustainable development of such new square of rainwater adjustment (group) storage system design and urban landscape environment. It is useful for the application of technology.

Design, Implementation, and Analysis of High-Speed Single-Stage N-Sorters and N-Filters

There is strong interest in developing high-performance hardware sorting systems which can sort a set of elements as quickly as possible. The fastest of the current FPGA systems are sorting networks, in which sets of 2-sorters operate in parallel in each series stage of a multi-stage sorting process. A 2-sorter is a single-stage hardware block which sorts two values, so any list with more than 2 values must be sorted with a series network of 2-sorters. A primary contribution of this work is to provide a general methodology for the design of stable single-stage hardware sorters which sort more than 2 values simultaneously. This general methodology for $N$ -sorter design, with $N{>}2$ , is then adapted for use in modern FPGAs, where it is shown that single-stage 3-sorters up to 9-sorters have speedup ratios from 2.0 to 3.5 versus the comparable state-of-the-art 2-sorter networks. A design system modification is shown to produce even faster single-stage $N$ -max and $N$ -min filters. When used for max pooling 32-bit data in the fastest analyzed FPGA, a single 9-max filter will process 500 million 9-pixel groups per second (4K:3840x2160 at 500 frames/second). The single-stage 9-median filter using this design methodology, useful in image processing, is shown to have speedup ratios of 3.0 to 4.1 versus state-of-the-art FPGA network implementations, even though its resource usage is comparable to, often better than, the network implementations. Ten 8-bit 9-median filters operating in parallel in the fastest FPGA will process over 5.4 billion pixels/sec (4K at over 600 frames/second).

RETRACTED: Consumer decision-making and smart logistics planning based on FPGA and convolutional neural network

In the fourth Industrial Revolution, cost-effective planning and rational management were the key to the success of the revolution. This paper mainly studies the development and application of models in machine learning technology. The abnormal activities monitored in real time are rectified so that the customer's electronic orders can be displayed through the support of big data, thus laying the foundation for the development of intelligent logistics. Under the data system, an exception model is created and classified and regressed. In this model, the security and stability of customer orders in the network can be automatically detected, and the abnormal data can be analyzed and evaluated. Unusual circumstances of this kind need to be in an intelligent logistics environment, and delivery tasks must be called intuitive for special care. Early detection of abnormal order events is expected to improve the accuracy of delivery planning. To enable new technical solutions, the logistics industry and economic decision-makers often lack the IT background and expertise needed to start developing new systems and technical solutions. Evaluate the benefits of using. Implementation and integration complexity is seen as one of the three major obstacles to the success of the IoT above. This is by hindering long-term investment in new technologies from slowing down digitization.

RETRACTED: Contribution rate measurement of scientific and technological progress based on FPGA and convolutional neural network

A logical and compelling form, tech-savvy innovation, creativity and personal growth measurement mode, cooperative test, review the consistency of the evolution of butterfly breakpoint test and pilot test. Special assessment strategies. According to Qingdao's yield information, experimental results show that the average level of commitment than the general logic and pace of mechanical progress Qingdao. The city has entered a serious stage of economic development. This is a common arrangement gift revealed by science, technological innovation and progress (STI) information and pointers, and agree with the classification rules and recommendations in order. It has been referred to as a "fractal family" actually, this arrangement of the manual is conspicuous manual. By referring to the Italian town, these documents are scientific and technical indicators of the OECD's work of experts that have been agreed upon by the state. Different points are involved in this configuration guide, for example, creation, progress exercises and STI-HR-related estimates, and to consider the new difficulties and improvements in various fields in periodic revision. The degree of alignment continues to expand with advances in this area.

RETRACTED: Light music online system based on FPGA and Convolutional Neural Network

In recent years, research in education and study abroad has focused on collaborative research between education and learning, for example, using “diversified education” and “flexible education” in the teaching process. Simultaneously, colleges in numerous nations likewise that undergrad instruction must address self-association and variation models in the training and learning measure. These advanced instructive thoughts and college strategies offer viable hypothetical help for this study. However, the traditional educational model of “diversity” and “cognitive flexibility” pays attention to the difference in student learning knowledge. Personal Career Goals: In other words, this model is designed from educational content instructions, ignoring key factors. It must be a difference in the actual meaning of the development of the “diversity” student personality. Therefore, despite the various social systems, the importance of reforms in foreign universities and education has improved, reflecting previous experimental educational effectiveness assessments, reflecting the development of traditional educational theories based on the FPGA and Convolutional Neural Network (CNN). Teach and summarize your experience. In Reality, it easy to find a universal educational model. Because the actual educational model comes from achieving educational goals, consensus can be obtained from numerous educational theories and practical studies.

Nonuniformity Correction Design and Implementation for Infrared Image Based on FPGA and Artificial Neural Networks

Infrared imaging technology is widely used in military and civilian applications. However, due to the materials and manufacturing technology, the response of each unit in the infrared detector is not completely consistent, which leads to the nonuniformity of the infrared focal plane array. In this article, we propose a way to use artificial neural network by self-adaptively updating the correction coefficients based on FPGA. Compared with traditional calibration-based method, our method is more flexible and can avoid the effects of temperature drift efficiently.

WITHDRAWN: Emotion recognition simulation of Japanese text based on FPGA and neural network

Abstract Text emotion recognition is an important task to identify the human reaction, with several solutions in various areas such as data mining, online learning, information filtering systems, Human-Computer Interaction, and psychology. Specific text emotional perception is the most solved problem in the literature. Hidden emotion recognition is to solve this problem, as it is the most difficult problem hidden in ordinary text. Therefore, the solution needs to understand the text in faster action, so the Neural Network (NN) is implemented in this system. The text recognition of Japanese language is difficult in existing methods like processing time is low, accuracy is high and power consumption is low in (Field Programmable Gate Array) FPGA based neural network classifier. This type of Neural Network (NN) analysis is beneficial to Japanese emotions as it implements the classification result so the accuracy is improved. To test this theory, an automatic emotional word recognition system uses the learning and text features and is based on classification. To analyze the performance of the proposed Neural Network (NN) like a flip-flop, power, latency, precision, recall, and F-measure. It turns out that recognition based on classification can significantly increase the result. Performance highlights of these methods and the impact of simple neural network tasks such as reduce the issues this also works for the best performance.

WITHDRAWN: Digital media vision innovation based on FPGA and Convolutional Neural Network

This article has been withdrawn: please see Elsevier Policy on Article Withdrawal ( https://www.elsevier.com/about/our-business/policies/article-withdrawal ). This article has been withdrawn at the request of the Editor in Chief. Subsequent to acceptance of this special issue paper by the responsible Guest Editor Sundhararajan Mahalingam, the integrity and rigor of the peer-review process was investigated and confirmed to fall beneath the high standards expected by Microprocessors & Microsystems. There are also indications that much of the Special Issue includes unoriginal and heavily paraphrased content. Due to a configuration error in the editorial system, unfortunately the Editor in Chief did not receive these papers for approval as per the journal's standard workflow.

WITHDRAWN: Collaborative system of industry, university and research institute based on FPGA and convolutional neural network

This article has been withdrawn: please see Elsevier Policy on Article Withdrawal (https://www.elsevier.com/about/our-business/policies/article-withdrawal). This article has been withdrawn at the request of the Editor in Chief. Subsequent to acceptance of this special issue paper by the responsible Guest Editor Sundhararajan Mahalingam, the integrity and rigor of the peer-review process was investigated and confirmed to fall beneath the high standards expected by Microprocessors & Microsystems. There are also indications that much of the Special Issue includes unoriginal and heavily paraphrased content. Due to a configuration error in the editorial system, unfortunately the Editor in Chief did not receive these papers for approval as per the journal's standard workflow.

WITHDRAWN: Smart classroom learning atmosphere monitoring based on FPGA and Convolutional Neural Network

This article has been withdrawn: please see Elsevier Policy on Article Withdrawal ( https://www.elsevier.com/about/our-business/policies/article-withdrawal ). This article has been withdrawn at the request of the Editor in Chief. Subsequent to acceptance of this special issue paper by the responsible Guest Editor Sundhararajan Mahalingam, the integrity and rigor of the peer-review process was investigated and confirmed to fall beneath the high standards expected by Microprocessors & Microsystems. There are also indications that much of the Special Issue includes unoriginal and heavily paraphrased content. Due to a configuration error in the editorial system, unfortunately the Editor in Chief did not receive these papers for approval as per the journal's standard workflow.

WITHDRAWN: Intelligent recognition of motion posture based on FPGA and neural network

This article has been withdrawn: please see Elsevier Policy on Article Withdrawal (https://www.elsevier.com/about/our-business/policies/article-withdrawal). This article has been withdrawn at the request of the Editor in Chief. Subsequent to acceptance of this special issue paper by the responsible Guest Editor Hameem Shanavas, the integrity and rigor of the peer-review process was investigated and confirmed to fall beneath the high standards expected by Microprocessors & Microsystems. There are also indications that much of the Special Issue includes unoriginal and heavily paraphrased content. Due to a configuration error in the editorial system, unfortunately the Editor in Chief did not receive these papers for approval as per the journal's standard workflow.

WITHDRAWN: Design of cultural creative products based on FPGA and convolutional neural network

This article has been withdrawn: please see Elsevier Policy on Article Withdrawal ( https://www.elsevier.com/about/our-business/policies/article-withdrawal ). This article has been withdrawn at the request of the Editor in Chief. Subsequent to acceptance of this special issue paper by the responsible Guest Editor Sundhararajan Mahalingam, the integrity and rigor of the peer-review process was investigated and confirmed to fall beneath the high standards expected by Microprocessors & Microsystems. There are also indications that much of the Special Issue includes unoriginal and heavily paraphrased content. Due to a configuration error in the editorial system, unfortunately the Editor in Chief did not receive these papers for approval as per the journal's standard workflow.