Negligible Threshold Voltage Shift Research Articles

Passivated indium oxide thin-film transistors with high field-effect mobility (128.3 cm2 V−1 s−1) and low thermal budget (200 °C)

Here, we demonstrate a high-mobility indium oxide (In2O3) thin-film transistor (TFT) with a sputtered alumina (Al2O3) passivation layer (PVL) with a low thermal budget (200 °C). The sputtering process of the Al2O3 PVL plays a positive role in improving the field-effect mobility (µ FE) and current on/off ratio (I ON/I OFF) performance of the In2O3 TFTs. However, these enhancements are limited due to the high density of intrinsic trap defects in the In2O3 channels, as reflected in their large hysteresis and poor bias stability. Treating the In2O3 channel with oxygen (O2) plasma prior to sputtering the Al2O3 PVL results in notable improvements. Specifically, a high µ FE of 128.3 cm2V−1 s−1, a high I ON/I OFF over 106 at V DS of 0.1 V, a small hysteresis of 0.03 V, and a negligible threshold voltage shift under negative bias stress are achieved in the passivated In2O3 TFT (with O2 plasma pretreatment), representing a significant improvement compared to the passivated In2O3 TFT (without O2 plasma pretreatment) and the unpassivated In2O3 TFT. The remarkable reduction of intrinsic trap defects in the passivated In2O3 TFT compensated by O2 plasma is the primary mechanism underlying the improvement in µ FE and bias stability, as validated by x-ray photoelectron spectra, hysteresis analysis, and temperature-stress electrical characterizations. Plasma treatment effectively compensates for intrinsic trap defects in oxide semiconductor (OS) channels, when combined with sputter passivation, resulting in a significant enhancement of the overall performance of OS TFTs under low thermal budgets. This approach offers valuable insights into advancing OS TFTs with satisfactory driving capability and wide applicability.

Interfacial Charge Transport Enhancement of Liquid-Crystalline Polymer Transistors Enabled by Ionic Polyurethane Dielectric.

In organic field-effect transistors (OFETs) using disordered organic semiconductors, interface traps that hinder efficient charge transport, stability, anddevice performance are inevitable. Benchmark poly(9,9-dioctylfuorene-co-bithiophene) (F8T2) liquid-crystalline polymer semiconductor has been extensively investigated for organic electronic devices due to its promising combination of charge transport and light emission properties. This study demonstrates that high-capacitance single-layered ionic polyurethane (PU) dielectrics enable enhanced charge transport in F8T2 OFETs. The ionic PU dielectrics are composed of a mild blending of PU ionogel and PU solution, thereby forming a solid-state film with robust interfacial characteristics with semiconductor layer and gate electrode in OFETs and measuring high capacitance values above 10 µF cm-2 owing to the combined dipole polarization and electric double layer formation. The optimized fabricated ionic PU-gated OFETs exhibit a low-voltage operation at -3V with a remarkable hole mobility of over 5 cm2 V-1 s-1 (average = 2.50 ± 1.18 cm2 V-1 s-1), which is the highest mobility achieved so far for liquid-crystalline F8T2 OFETs. This device also provides excellent bias-stable characteristics in ambient air, exhibiting a negligible threshold voltage shift of -0.03V in the transfer curves after extended bias stress, with a reduced trap density.

Nano-Scale Ga2O3 Interface Engineering for High-Performance of ZnO-Based Thin-Film Transistors

Thin-film transistor (TFT) is a essential device for future electronics driving the next level of digital transformation. The development of metal-oxide-semiconductor (MOS) TFTs is considered one of the most advantageous devices for next-generation, large-area flexible electronics. This study demonstrates the systematic study of the amorphous gallium oxide (a-Ga2O3) and its application to nanocrystalline ZnO TFTs. The TFT with a-Ga2O3/c-ZnO-stack channel exhibits a field-effect mobility of ∼41 cm2 V-1 s-1 and excellent stability under positive-bias-temperature stress. The a-Ga2O3/c-ZnO-stack TFT on polyimide (PI) substrate exhibits a negligible threshold voltage shift upon 100k bending cycles with a radius of 3 mm and is very stable under environmental test. The smooth morphology with tiny grains of ∼12 nm diameter with fewer grain boundary states improves the charge transport in Ga2O3/ZnO-stack TFT. The existence of amorphous a-Ga2O3 in between very thin ZnO layers helps to enhance the heterointerfaces and reduce the defect density in Ga2O3/ZnO interface. Therefore, integrating a-Ga2O3 in the ZnO channel in stacked TFT can increase mobility and enhance stability for next-generation flexible TFT electronics.

Low Cost, Al2O3 and ZrAlOx Stack Passivation by Spray Pyrolysis for Highly Stable Amorphous InGaZnO Thin‐Film Transistors

AbstractA stack passivation by spray pyrolysis is demonstrated for high performance and stable amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs). The device performances and stabilities of a‐IGZO TFTs are compared with single zirconium‐aluminium‐oxide (ZAO), aluminium oxide (Al2O3), and stack ZAO/Al2O3 and Al2O3/ZAO passivation layers. The a‐IGZO TFTs with Al2O3/ZAO stack exhibit high performance and excellent stabilities under electrical, thermal, and environmental tests with negligible threshold voltage shift. The origin of the device performances and improved stabilities are analyzed using X‐ray photoelectron spectroscopy and high‐resolution transmission electron microscopy analyses. It is found that the Zr elements diffuse into the a‐IGZO channel when ZAO is directly deposited on the a‐IGZO, resulting in the deterioration of the device performance. It is also found that the Al2O3 single layer on top of the a‐IGZO cannot protect the back‐channel from moisture diffusion. But a thin Al2O3 layer on top of the TFTs can protect the diffusion of Zr elements from ZAO into the a‐IGZO channel and enhances the performance and stabilities. Therefore, the low cost, Al2O3/ZAO stack by spray pyrolysis on the sputtered a‐IGZO can be an excellent passivation for highly stable metal‐oxide TFTs.

CMOS-compatible GaN-based high electron mobility transistors with gate-first technology

In this article, the gate-first technology was developed in GaN-based HEMTs on silicon with low-temperature (LT) Ta/Al/CuW ohmic contacts. Benefiting from the 20 nm high-quality in-situ SiNx layer, the gate-first device with LT Ta/Al/ CuW ohmic contacts shows a maximum dielectric electric field strength of 13.5 MV/cm and a high Baliga’ Figure of Merit (BFOM) of 424 MW/cm2, which is 20.5% and 61.8% higher than that of the gate-first device with high-temperature (HT) Ti/Al/Ni/Au ohmic contacts, respectively. Moreover, the proposed device also demonstrates a negligible threshold voltage shift based on different gate stress bias and stress time measurements. By fitting the data with a power law, the lifetime was extrapolated to 63.2% of failures at 25 °C after 20 years, resulting in operating gate voltages of 9.2 V and 11.1 V (about 4.6 MV/cm and 5.6 MV/cm) for the gate-first devices with HT Ti/Al/Ni/Au and LT Ta/Al/CuW ohmic contacts, respectively. These results illustrate that the gate-first device with LT Au-free ohmic contacts has great potential in high-voltage applications.

Polycrystalline InGaO Thin-Film Transistors with Coplanar Structure Exhibiting Average Mobility of ≈78 cm2 V-1 s-1 and Excellent Stability for Replacing Current Poly-Si Thin-Film Transistors for Organic Light-Emitting Diode Displays.

Highly ordered polycrystalline indium gallium oxide (PC-IGO) film is obtained by the crystallization of room temperature sputtered amorphous IGO on a hot plate at 350°C for 1 h and then annealed for 1 h in an N2 O environment. A high-density PC-IGO of ≈7.15g cm-3 with reduced oxygen vacancy (≈14.83%) and hydroxyl (OH) related defects (≈10.96%) has been obtained by N2 O annealing. Self-aligned coplanar thin-film transistor (TFT) with the PC-IGO exhibits the average saturation mobility of 78.73 cm2 V-1 s-1 , threshold voltage of -1.07V, subthreshold swing of 0.147V dec-1 , and the on/off current ratio of over 108 . The TFTs show excellent stability under bias-temperature stress with a negligible threshold voltage shift (ΔVTH ) of + 0.1 and -0.1V for the positive and negative bias stresses, respectively. The TFTs exhibit very stable environmental stability when the TFTs are stored under high humidity (85%) and a high temperature (85°C) for 2 days. The ring oscillator and the gate driver mode of the PC-IGO TFTs exhibit the propagation delay of 7.44ns/stage with rising/falling times of less than 0.7 μs, respectively. Therefore, the PC-IGO TFTs are suitable for large area, high-resolution active-matrix organic, and inorganic light-emitting diodes displays.

Improvement of metal-oxide films by post atmospheric Ar/O2 plasma treatment for thin film transistors with high mobility and excellent stability

Metal-oxide thin-film transistors (MO TFTs) with suitable device performances such as high field-effect mobility (μ FE), low subthreshold swing, high ON/OFF current ratio, and excellent stability under bias stress are of increasing attention for the applications to displays and flexible electronics. Here, we introduce the effect of post atmospheric Ar/O2 plasma (AAP) on spray-pyrolyzed MO film and its role in realizing the high-performance TFT. To better understand the physicochemical mechanism, the spectroscopic, morphologic, and electrical properties of the MO films were studied. From the X-ray photoelectron spectroscope (XPS) results, the composition ratios for Zn:La:O in AAP-treated LaZnO are 4.97:1.00:7.65 before treatment, 5.01:1.00:8.58 upon 5 cycles treatment, and 4.68:1.00:9.72 for 10 cycle treatment. The LaZnO TFT mobilities for 0, 5 and 10 cycles treatment are 8.64, 20.13, and 8.96 cm2 V−1 s−1, respectively. The AAP-treatment on the MO layer could improve the saturation mobility of ZnO, LaZnO, HfZnO, and LiZnO TFTs from 11.65, 8.95, 4.46, and 33.50 cm2 V−1 s−1 to 23.64, 20.13, 12.56, and 48.47 cm2 V−1 s−1, respectively. Furthermore, the optimal TFT shows excellent stability under positive (negative) bias temperature stress (PBTS and NBTS) with a negligible threshold voltage shift.

8‐2: Low Cost Manufacturing of AlZnO/ZnO Thin Film Transistor with High Mobility Over 80 cm2/Vs and Positive Threshold Voltage by Spray Pyrolysis

We demonstrate the low‐cost AlZnO/ZnO TFT by spray pyrolysis at 350 °C. High field‐effect mobility is achieved over 80 cm2/V.s with a subthreshold slope of 123 mV/decade. The higher mobility is due to the 2D like electron gas at the interface of AlZnO/ZnO. The stack TFT shows positive threshold voltage and negligible threshold voltage shift under positive bias stress. The presence of Al‐O at the interface reduces the oxygen vacancies and improves the bias stability.

1300 V Normally-OFF p-GaN Gate HEMTs on Si With High ON-State Drain Current

In this article, we demonstrate normally-OFF p-GaN gate high electron mobility transistors (HEMTs) on Si with an ultrahigh breakdown voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{BR}$ </tex-math></inline-formula> ) and excellent saturation drain current. Benefiting from the optimized material growth of high-resistivity buffer, effective Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> surface passivation with suppressed OFF-state leakage current, and proper management of the electric field on the p-GaN gate edge, the device with a gate–drain distance of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$18.5~\mu \text{m}$ </tex-math></inline-formula> exhibits a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{BR}$ </tex-math></inline-formula> of 1344 V at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{D}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1~\mu \text{A}$ </tex-math></inline-formula> /mm with grounded substrates, the highest among all the reported normally-OFF GaN-on-Si transistors. Well-restored high-density 2-D electron gas and efficient gate modulation enable the device with a high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{DS,max}$ </tex-math></inline-formula> of 450 mA/mm and a low specific ON-resistance of 3.92 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Moreover, a large threshold voltage of 1.6 V (at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{D}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10~\mu \text{A}$ </tex-math></inline-formula> /mm) and a steep subthreshold slope of 66 mV/dec have been achieved, with negligible threshold voltage shift upon long-term forward gate stress at 150 °C. These results illustrate the great potential of p-GaN gate HEMTs on Si for beyond 600-V applications.

Extremely Stable, High Performance Gd and Li Alloyed ZnO Thin Film Transistor by Spray Pyrolysis

AbstractThe simultaneous doping effect of Gadolinium (Gd) and Lithium (Li) on zinc oxide (ZnO) thin‐film transistor (TFT) by spray pyrolysis using a ZrOx gate insulator is reported. Li doping in ZnO increases mobility significantly, whereas the presence of Gd improves the stability of the device. The Gd ratio in ZnO is varied from 0% to 20% and the Li ratio from 0% to 10%. The optimized ZnO TFT with codoping of 5% Li and 10% Gd exhibits the linear mobility of 25.87 cm2 V−1 s−1, the subthreshold swing of 204 mV dec−1, on/off current ratio of ≈108, and zero hysteresis voltage. The enhancement of both mobility and stability is due to an increase in grain size by Li incorporation and decrease of defect states by Gd doping. The negligible threshold voltage shift (∆VTH) under gate bias and zero hysteresis are due to the reduced defects in an oxide semiconductor and decreased traps at the LiGdZnO/ZrOx interface. Li doping can balance the reduction of the carrier concentration by Gd doping, which improves the mobility and stability of the ZnO TFT. Therefore, LiGdZnO TFT shows excellent electrical performance with high stability.

Threshold voltage shift-proof circular oxide thin film transistor with top and bottom gates for high bending stability

Negligible threshold-voltage shift is reported for oxide thin-film transistors (TFTs) under high current (3 μA) and tensile bending stress (2 mm radius). The good stability is attributed to a circular TFT structure with electrically shorted top and bottom gates, and a polyimide substrate embedded with carbon-nanotubes for mechanical support and damage-free detachment from carrier glass. The circular structure leads to uniform electric field distribution across the channel, hard saturation in output characteristics, independence from tensile bending direction-related degradation, as well as isolation of the channel from stress concentrated points, which arise from local electric-field crowding at sharp corners or channel edges. The double-gate topology increases gate-drivability and achieves volume-accumulation, which minimizes the influence of defects at the channel surface and slight variations in carrier concentration during stress. Furthermore, the presence of two gates slightly shifts the location of the neutral bending plane towards the oxide semiconductor, thereby significantly reducing strain.

Remarkable Stability Improvement of ZnO TFT with Al2O3 Gate Insulator by Yttrium Passivation with Spray Pyrolysis

We report the impact of yttrium oxide (YOx) passivation on the zinc oxide (ZnO) thin film transistor (TFT) based on Al2O3 gate insulator (GI). The YOx and ZnO films are both deposited by spray pyrolysis at 400 and 350 °C, respectively. The YOx passivated ZnO TFT exhibits high device performance of field effect mobility (μFE) of 35.36 cm2/Vs, threshold voltage (VTH) of 0.49 V and subthreshold swing (SS) of 128.4 mV/dec. The ZnO TFT also exhibits excellent device stabilities, such as negligible threshold voltage shift (∆VTH) of 0.15 V under positive bias temperature stress and zero hysteresis voltage (VH) of ~0 V. YOx protects the channel layer from moisture absorption. On the other hand, the unpassivated ZnO TFT with Al2O3 GI showed inferior bias stability with a high SS when compared to the passivated one. It is found by XPS that Y diffuses into the GI interface, which can reduce the interfacial defects and eliminate the hysteresis of the transfer curve. The improvement of the stability is mainly due to the diffusion of Y into ZnO as well as the ZnO/Al2O3 interface.

Aqueous-solution-driven HfGdOx gate dielectrics for low-voltage-operated α-InGaZnO transistors and inverter circuits

In this work, a non-toxic and environmentally friendly aqueous-solution-based method has been adopted to prepare gadolinium-doped hafnium oxide (HfO2) gate dielectric thin films. By adjusting the gadolinium (Gd) doping concentration, the oxygen vacancy content, band offset, interface trap density, and dielectric constant of HfGdOx (HGO) thin films have been optimized. Results have confirmed that HGO thin films with Gd doping ratio of 15 at.% have demonstrated appropriate dielectric constant of 27.1 and lower leakage current density of 5.8 × 10−9 A cm-2. Amorphous indium-gallium-zinc oxide (α-IGZO) thin film transistors (TFTs) based on HGO thin film (Gd: 15 at.%) as gate dielectric layer have exhibited excellent electrical performance, such as larger saturated carrier mobility (μsat) of 20.1 cm2 V-1 S-1, high on/off current ratio (Ion/Ioff) of ∼108, smaller sub-threshold swing (SS) of 0.07 V decade-1, and a negligible threshold voltage shift (△VTH) of 0.08 V under positive bias stress (PBS) for 7200 s. To confirm its potential application in logic circuit, a resistor-loaded inverter based on HGO/α-IGZO TFTs has been constructed. A high voltage gain of 19.8 and stable full swing characteristics have been detected. As a result, it can be concluded that aqueous-solution-driven HGO dielectrics have potential application in high resolution flat panel displays and ultra-large-scale integrated logic circuits.

Donor unit effect on DPP based organic field-effect transistor performance

We report diketopyrrolopyrrole (DPP) based copolymers, poly (diketopyrrolopyrrole-cyclopentadithiophene) (PDPPTT-CPDT) and poly(diketopyrrolopyrrolebenzo[1,2-b:4,5-b’]dithiophene) (PDPPTT-BDT) to investigate donor unit structure effects on organic field-effect transistor (OFET) performance. The highest occupied molecular orbital (HOMO) level and copolymer band gap were tuned by introducing different donor units on the acceptor DPP backbone. PDPPTT-BDT OFETs show 10 fold higher hole field-effect mobility, up to 0.08 cm2 V−1 s−1, than PDPPTT-CPDT OFETs due to better crystallinity and higher HOMO energetic levels. PDPPTT-CPDT and PDPPTT-BDT were operationally stable with negligible threshold voltage shift after cycling.

Isoindigo benzodifurandione based conjugated polymers for high performance organic field-effect transistors

We report isoindigo based copolymers, poly(isoindigo benzodifurandione-bithiophene-alkoxyl) (PIBDF-BTO) and poly(isoindigo-bithiophene-alkoxyl) (PI-BTO) for high performance organic field-effect transistors (OFETs).

Reduction of Bias and Light Instability of Mixed Oxide Thin-Film Transistors

Despite their potential use as pixel-switching elements in displays, the bias and light instability of mixed oxide semiconductor thin-film transistors (TFTs) still limit their application to commercial products. Lack of reproducible results due to the sensitivity of the mixed oxides to air exposure and chemical contamination during or after fabrication hinders any progress towards the achievement of stable performance. Consequently, one finds in literature several theories and mechanisms, all justified, but most of them conflict despite being on the same subject matter. In this study, we show that under an optimized fabrication process, which involves the in situ passivation of a mixed oxide semiconductor, we can reduce the bias and light instability of the mixed-oxide semiconductor TFTs by decreasing the semiconductor thickness. We achieve a negligible threshold voltage shift under negative bias combined with light illumination stress when the mixed oxide semiconductor thickness is around three nanometers. The improvement of stability in the thin mixed-oxide semiconductor TFTs is due to a reduced number of oxygen-vacancy defects in the bulk of the semiconductor, as their total number decreases with decreasing thickness. Under the optimized fabrication process, bulk, rather than interfacial defects, thus seem to be the main source of the bias and light instability in mixed oxide TFTs.

Photosensitivity of InZnO thin-film transistors using a solution process

Oxide semiconductor devices play a role in both switches and photo-sensors in interactive displays. During the fabrication of oxide semiconductor devices, the sol-gel solution process that is used to form an oxide semiconductor has various merits, including its simplicity and low cost as well as its good composition controllability. Here, we present the photosensitivity characteristics of an oxide photo thin-film transistor (TFT) created using the InZnO (IZO) sol-gel process. Upon exposure to light, photocurrent (Iphoto) in the negative gate bias regime is significantly increased with a negligible threshold voltage shift. The photosensitivity is modulated by geometrical factors and by the IZO material composition. We observed a significant effect of the channel thickness and IZO composition on the photosensitivity, which was attributed to the screening effect of optically ionized oxygen vacancies (Vo++). In particular, the optimized bi-layered oxide photo-TFT presents a good Iphoto/Idark photosensitivity value of 3 × 104 and a subthreshold slope of 0.96 V/decade. In addition, the persistent photoconductivity of the oxide photo-TFT was removed by applying positive gate voltage, resulting in good high-speed operation. These results taken together demonstrate that the IZO photo-TFT produced by the sol-gel process can be workable when applied to interactive displays.

Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al2O3 gate dielectric

Low-temperature atomic layer deposition (ALD) was employed to deposit Al2O3 as a gate dielectric in amorphous In–Ga–Zn–O thin-film transistors fabricated at temperatures below 120 °C. The devices exhibited a negligible threshold voltage shift (ΔVT) during negative bias stress, but a more pronounced ΔVT under positive bias stress with a characteristic turnaround behavior from a positive ΔVT to a negative ΔVT. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive ΔVT, which can be fitted using the stretched exponential function. The breakage of residual AlO-H bonds in low-temperature ALD Al2O3 is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In–Ga–Zn–O channel and induce the negative ΔVT through electron doping with power-law time dependence. A rapid partial recovery of the negative ΔVT after stress is also observed during relaxation.

Model for threshold voltage instability in top-gated nanocrystalline silicon thin film transistor

The analytical model for the threshold voltage instability in top-gated staggered nanocrystalline silicon thin-film transistor is reported. This novel model includes the effect of various physical parameters like grain size, gate insulator thickness, doping density and grain boundary trapping state on the threshold voltage shift which is never reported earlier. It is observed that the higher trap density, greater doping concentration and larger gate insulator thickness provide lesser threshold voltage shift. Further, it is found from the results of grain size analysis that if grain size is smaller than threshold voltage shift decreases with decrease in grain size. However, if grain size is larger $$(\hbox {D}_\mathrm{g} > 20\,\hbox {nm})$$(Dg>20nm) then device become stable and shows negligible threshold voltage shift. In this paper, threshold voltage shift under gate bias voltage is also analyzed and result reveals that threshold voltage increases with the bias voltage. The calculated results are compared with experimental data. The close match between the two confirms the validity of proposed study.

100-nm-size ferroelectric-gate field-effect transistor with 108-cycle endurance

The fabrication process of 100-nm-size ferroelectric-gate field-effect transistors (FeFETs) with high endurance was reported. The FeFETs had Pt/Sr0.8Ca0.2Bi2Ta2O9 (SCBT)/HfO2/Si stacks where the Pt gate length was 100 nm. The FeFETs were successfully fabricated by integrating many technologies such as fine patterning of etching masks by electron-beam lithography, precise anisotropic etching of the gate stacks, well-controlled ion implantation for gate-self-aligned sources and drains, and the sidewall-cover process that we had developed. Good performances of the FeFETs were characterized by the endurance of 108 program-and-erase cycles with negligible threshold-voltage shift and good drain-current retention for 3.98 × 105 s.