Negative Bias Temperature Instability Mechanism Research Articles

Comparative Analysis of Hot Carrier Degradation (HCD) in 10-nm Node nMOS/pMOS FinFET Devices

In 10-nm node core FinFETs, we analyzed the cause of higher hot carrier degradation (HCD) in pFinFETs than in nFinFETs. Self-heating effect is severe in pFinFETs because SiGe is used as the source/drain materials, which makes the device temperature higher than nFinFETs. Theoretically, because the lifetime of multiple particle (MP) mechanism decreases as temperature increases, degradation due to MP decreases. Therefore, it is difficult for the pure HCD mechanisms to occur more in pFinFETs, which has higher temperature than nFinFETs. However, in pFinFETs, unlike nFinFETs, interface traps can be generated due to negative-bias temperature instability (NBTI) that occurs by the reaction between inversion holes and electrons of Si-H bonds. Also, since NBTI deteriorates more as the temperature increases, the phenomenon of higher degradation in pFinFET than nFinFET can be explained with the NBTI mechanism. Therefore, we propose an additional NBTI mechanism that is caused by high device temperature in pFinFETs even in the HCD condition. In addition, the main components were investigated through measurements of current degradation rate in various voltage conditions, and it was found that NBTI is dominant in pFinFETs. Finally, NBTI that can occur in the HCD condition was predicted through technology computer-aided design (TCAD) simulation. As a result, degradation due to pure hot carriers without NBTI occurs more in nFinFETs than in pFinFETs.

Influence of Design and Process Parameters of 32-nm Advanced-Process High-k p-MOSFETs on Negative-Bias Temperature Instability and Study of Defects

Negative-bias temperature instability (NBTI) has become a prominent factor limiting scaling of complementary metal–oxide–semiconductor technology. This work presents a comprehensive simulation study on the effects of critical design parameters of 32-nm advanced-process high-kp-channel metal–oxide–semiconductor field-effect transistors on NBTI. The NBTI mechanism and defects were explored for various geometric and process design parameters over a wide range of values. The NBTI simulation method applied in this work follows the on-the-fly method to capture the mechanisms of fast and slow traps. This work illustrates the dependence of the threshold voltage (Vth) degradation on the stress oxide field and stress temperature as well as investigation of the Arrhenius plot for the devices. The temperature insensitivity during short stress time of 1 ms indicates absence of generated defects and presence of preexisting defects. It is also observed that significant defects are generated in the gate stack subsequent to NBTI. The slope obtained from the Vth degradation analysis at 1 ks and 375°C shows that changing the SiO2 interfacial layer thickness affects the Vth degradation by 96.16% more than changing the HfO2 thickness and by 80.67% more than changing the metal gate thickness. It is also found that the NBTI effect depends on process design considerations, specifically the boron concentration in the highly doped drain, the metal gate work function, and the halo doping concentration; it was observed that higher boron dose and high metal work function may lead to higher Vth degradation. However, the halo doping concentration in the advanced 32-nm structure has an insignificant effect on NBTI.

Consistency of the Two Component Composite Modeling Framework for NBTI in Large and Small Area p-MOSFETs

Consistency of the recently proposed deterministic composite modeling framework for Negative Bias Temperature Instability (NBTI) in large area devices is verified for stochastic NBTI in small area devices. The framework has two independent and uncoupled components, interface trap generation ( $\Delta V_{\mathrm {\mathbf {IT}}}$ ), and hole trapping in pre-existing defects ( $\Delta V_{\mathrm {\mathbf {HT}}}$ ). The time evolution of mean threshold voltage shift ( $\Delta V_{T}$ ), from multiple ultra-fast measurements in small area devices under diverse stress and recovery conditions, is predicted by the deterministic composite framework. It is shown that although the physical mechanism of NBTI remains the same as the device area is scaled, there can be significant differences in the relative $\Delta V_{\mathrm {\mathbf {IT}}}$ and $\Delta V_{\mathrm {\mathbf {HT}}}$ contribution to $\Delta V_{T}$ between large and small area devices, which can alter the overall model parameters. A stochastic simulation framework, fully consistent with the deterministic framework, is developed, which is shown to predict experimentally measured mean time evolution of $\Delta V_{T}$ in small area devices.

Universal framework for temperature dependence prediction of the negative bias temperature instability based on microscope pictures

A universal framework for describing the temperature enhanced negative bias temperature instability (NBTI) is developed in this paper. Analytical time evolution models of the NBTI mechanisms, as Pb center generation and hole-transport in the oxygen vacancies, are proposed based on careful investigation of atom-level microscopic pictures. A logarithmic time function is derived to describe the interface state (Pb center) generation and recovery evolution by revealing a fact that the activation energy is significantly modified by the accumulation of generated defects. Corresponding coefficients, including the generation amplitudes and time constant, are identified depending on temperature linearly and exponentially. Moreover, the unrecoverable oxide hole-trapping is proposed resulted from the hole-transport among deep-level oxygen vacancies driven by electrical field within the gate oxide. A power-law time function is derived to describing this evolution, with time exponent linear to temperature. Parameters calculated by the proposed analytical models reveal good consistent with the parameters directly extracted from the measured data, indicating the validation and universality of the physical based framework in reproducing the parametric shift of the NBTI degradation under various temperature conditions and process technologies.

Lifetime Reliability Enhancement of Microprocessors

Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling and increasing temperatures due to growing power density are threatening lifetime reliability. Negative bias temperature instability (NBTI) has been known for decades, but its impact has been insignificant compared to other factors. Aggressive scaling, however, makes NBTI the most serious threat to chip lifetime reliability in today's and future process technologies. The delay of microprocessors gradually increases as time goes by, due to stress and recovery phases. The delay eventually becomes higher than the value required to meet design constraints, which results in failed systems. In this article, the mechanism of NBTI and its effects on lifetime reliability are presented, then various techniques to mitigate NBTI degradation on microprocessors are introduced. The mitigation can be addressed at either the circuit level or architectural level. Circuit-level techniques include design-time techniques such as transistor sizing and NBTI-aware synthesis. Forward body biasing, and adaptive voltage scaling are adaptive techniques that can mitigate NBTI degradation at the circuit level by controlling the threshold voltage or supply voltage to hide the lengthened delay caused by NBTI degradation. Reliability has been regarded as something to be addressed by chip manufacturers. However, there are recent attempts to bring lifetime reliability problems to the architectural level. Architectural techniques can reduce the cost added by circuit-level techniques, which are based on the worst-case degradation estimation. Traditional low-power and thermal management techniques can be successfully extended to deal with reliability problems since aging is dependent on power consumption and temperature. Self-repair is another option to enhance the lifetime of microprocessors using either core-level or lower-level redundancy. With a growing thermal crisis and constant scaling, lifetime reliability requires more intensive research in conjunction with other design issues.

A Study of High-Voltage p-Type MOSFET Degradation Under AC Stress

In this paper, the degradation characteristics of high-voltage (HV) p-type MOSFETs are investigated during negative unipolar ac stress on the gate electrode. The threshold voltage under ac stress is shifted gradually by both the negative-bias temperature-instability mechanism and Fowler-Nordheim degradation. We qualitatively analyze the degradation characteristics of HV p-type MOSFETs under ac stress, and observe the threshold voltage saturation for HV p-type MOSFETs at long ac stress. Based on the effects of temperature and duty cycles, we offer a suitable model of degradation saturation after long ac stress, which is caused by interface trap saturation and recovery during pulse delay timing, which is dependent on thermal activation energy.

Defect Generation Mechanism and Its Impact on Reliability Properties in MONOS Devices

Introduction Metal-oxide-nitride-oxide-semiconductor (MONOS) device attracts much attention owing to its potential as future nonvolatile memory devices. For the use of MONOS devices, it is important to understand accurately the mechanism of reliability degradation induced by electrical stress such as programming and erasing. In this paper, we discuss the defects-generation mechanisms by using evaluation technique that we developed. We also show how the defects generation influences to reliability properties of the MONOS devices. Interface-State Generation by Program/Erase Cycling Program/Erase (P/E) cycle stress generates defects in MONOS devices and degrades their performance and reliability. Since it has been recognized for the MONOS devices that the degradation is mainly due to interface-state generation, we examined the mechanism of interface-state generation in the MONOS devices under P/E stress by using a charge measurement technique we developed. The amount of interface states (ΔNit) is found to have a strong correlation with charges flowing during erasing, irrespective of pulse voltage, pulse width and number of P/E cycles. It is further demonstrated that the ΔNit increases as hole current dominates in erasing, suggesting that hole injection from Si substrate during erasing is the main cause for the ΔNit. Data Retention Degradation Caused by Stress Induced Hole Current Data retention measurements after P/E cycle stress were carried out with applying gate voltage to control the direction of electron leakage during retention. As a result, higher charge loss was observed when applying negative gate voltage during retention, indicating that P/E stress-induced leakage current (SILC) across the tunnel oxide layer degrades the data retention.To detect the SILC directly, we performed carrier separation I-V measurement for p-channel MONOS devices. The tail of electron detrapping current at low voltage (electron SILC) was, however, observed only for the MONOS with highly Si-rich SiN charge trapping layer. Thus, a mechanism other than the electron SILC must be involved in the data retention degradation for the MONOS devices. The carrier separation measurements further demonstrated that hole current injected into the MONOS devices is increased after P/E cycle stress, indicating the existence of “hole SILC”. The hole SILC is found to be determined by the ΔNit regardless of MONOS structure, suggesting that the hole SILC is attributable to the generated interface states. These results suggest a mechanism for the data retention degradation caused by P/E cycle stress: The P/E cycle stress damages tunnel oxide layer and generates the ΔNit. The hole SILC is injected via the ΔNit, degrading data retention through hole trapping and possible subsequent recombination with stored electrons. Impact of Interface-State Recovery on Reliability Properties It is well known, in the research field of MOS reliability, that accumulated holes attack Si-H bonds at the Si/SiO2 interface and induce negative bias temperature instability (NBTI). Since the ΔNit in the MONOS devices is generated by holes accumulated in Si substrate, it is speculated that physical origin of the ΔNit is similar to that in MOS devices, that is, Si-H bond dissociation. The Reaction-Diffusion (R-D) model, which explains well the NBTI mechanism, suggests that hydrogen released by the Si-H dissociation diffuses back to the interface and passivates the generated interface states after removal of electrical stress. It was observed for the MONOS devices that the ΔNit was found to be decreased after 200ºC 1h baking, demonstrating that the ΔNit is due to dissociation of Si-H bonds. Since the recovery accompanies the threshold voltage shift, suppression of the ΔNit is important for data retention property as well as for endurance property. Conclusions We have investigated the mechanisms for interface-state generation by P/E cycle stress, and demonstrated that holes injected from Si substrate is the main cause for the ΔNit. It is also found that the hole SILC is injected via the ΔNit, degrading data retention property through hole trapping and possible subsequent recombination with stored electrons. Since the physical origin of the ΔNit is Si-H bond breakage, a part of released hydrogen diffuses back to the interface and passivates the ΔNit, leading to the degradation of data retention property.

Recovery and universality in NBTI

The fast recovery behavior in negative bias temperature instability (NBTI) in SiON gate p-type metal–oxide–silicon field effect transistors was investigated. The fast recovery is due to the hole detrapping from the K-center (N3Si, where denotes a dangling bond). The Gaussian function-like hole trap energy level distribution explains the universality in the fast recovery. The results shed light on the NBTI mechanism.

Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation

As technology scales, Negative Bias Temperature Instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, we first investigate the impact of NBTI on PMOS devices and propose a temporal performance degradation model that considers the temperature variation between active and standby mode. We then discuss the resemblance between NBTI and leakage mechanisms, and find out that the impact of input vector and internal node on leakage and NBTI is different; hence, leakage and NBTI should be optimized simultaneously. Based on this, we study the impact of standby leakage reduction techniques (including input vector control and sleep transistor insertion) on circuit performance degradation considering active and standby temperature differences. We demonstrate the potential mitigation of the circuit performance degradation by these techniques.

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal–oxide–semiconductor field-effect transistors

Negative Bias Temperature Instability (NBTI) has become one of the most serious reliability problems of metal-oxide-semiconductor field-effect transistors (MOSFETs). The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25–0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H+ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H+ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H+ generated during NBTI stress.

Pulse stress frequency dependence of negative bias temperature instability in SiON gate transistors

Dependence of negative bias temperature instability (NBTI) on the frequency of the pulsed stress applied on p-channel transistors with plasma nitrided SiON gate dielectrics is studied. The threshold voltage shift (ΔVth) decrease is observed with increase in frequency. The fractional relaxation is found to be more remarkable after a pulse stress with higher frequency. A phenomenological model based on the dispersive transport of hydrogen in the gate dielectrics is proposed to explain the pulse based NBTI characteristics. The frequency dependence of NBTI is attributed to the existence of deep level hydrogen traps in the gate dielectrics. The model predicts reduced frequency dependence in the ultrahigh frequency range. The results and discussion also confirm the overall correctness of the dispersive transport framework in interpreting the NBTI mechanisms.

Understand NBTI Mechanism by Developing Novel Measurement Techniques

Our recent investigations and understanding of the negative bias temperature instability (NBTI) degradation in p-MOSFETs with ultrathin SiON gate dielectric are reviewed. The progressive understanding of NBTI mechanism is mainly related to the novel measurement techniques we developed. We show in this paper the following: 1) For the conventional charge pumping and direct-current current-voltage interface trap measurement, the interface trap density N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> is underestimated due to the recovery during measurement delay. The existing N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> data should be reexamined; 2) an ultrafast pulsed I-V method [fast pulsed measurement (FPM)] is developed to measure DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> with measurement time t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> = 100 ns. It can be considered as free from recovery during measurement; 3) due to the degradation during the initial threshold voltage measurement, the existing slow on-the-fly (OTF) DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> measurement distorts (overestimates) the slope and induces a kink at early stress time in the Log-Log curve of the time evolution of NBTI degradation. A fast OTF DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> measurement method is developed to overcome this problem; 4) a novel OTF interface trap (OFIT) measurement method is developed which is free from interface trap recovery during measurement. The OFIT measurement provides the most reliable data to inspect the interface trap R-D model; 5) combining the OFIT and FPM measurements, we decompose the NBTI DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> into two components: A slow DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sup> component contributed by with a slow recovery time longer than 50mus and a fast DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sup> component contributed by DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> with a broad spectrum of recovery time, including a component with very fast recovery time (100 ns); and 6) the dynamic degradation by DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sup> component is frequency-independent and can be measured by a dc method, whereas the dynamic degradation DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sup> by component measured by FPM is increased by increasing frequency. The ten-year lifetime of the p-MOSFETs is mainly determined by the degradation of the DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sup> component.

Atomic-scale defects involved in the negative-bias temperature instability

This paper examines the atomic-scale defects involved in a metal-oxide-silicon field-effect-transistor reliability problem called the negative-bias temperature instability (NBTI). NBTI has become the most important reliability problem in modern complementary-metal-oxide-silicon technology. Despite 40 years of research, the defects involved in this instability were undetermined prior to this paper. We combine DC gate-controlled diode measurements of interface-state density with two very sensitive electrically detected magnetic-resonance measurements called spin-dependent recombination (SDR) and spin-dependent tunneling (SDT). An analysis of these measurements provides an identification of the dominating atomic-scale defects involved in NBTI in pure- and plasma-nitrided oxide (PNO)-based devices. We are also able to observe atomic-scale defects involved in HfO2-based devices (although a definitive identification of the dominating defects structure was not possible). Our results in pure- devices indicate an NBTI mechanism which is dominated by the generation of Pb0 and Pb1 interface-state defects. (Pb0 and Pb1 are both silicon dangling-bond defects, in which the central silicon is back-bonded to three other silicon atoms precisely at the interface). This observation is consistent with what most NBTI researchers have assumed. However, our observations in PNO devices contradict with what most NBTI researchers had previously assumed. We demonstrate that the dominating NBTI-induced defect in the plasma-nitrided devices is fundamentally different than those observed in pure-based devices. Our measurements indicate that the new plasma-nitrided NBTI-induced defect's physical location extends into the gate dielectric. The defect participates in both SDR and SDT. Our SDR results strongly indicate that the plasma-nitrided defect has a density of states which is more narrowly peaked than that of centers and is near the middle of the band gap. The high sensitivity of our SDT measurements allow an identification of the physical and chemical nature of this defect through observations of hyperfine interactions. The defects are silicon dangling bonds, in which the central silicon is back-bonded to nitrogen atoms. We call these NBTI-induced defects centers because of the similarities to the centers observed in silicon nitride (the silicon-nitrided center is also a silicon dangling bond in which the silicon atom is back-bonded to nitrogen atoms). The defect identification in plasma-nitrided devices helps to explain the following phenomena: (1) NBTI's enhancement in plasma-nitrided devices; (2) conflicting reports of NBTI-induced interface states and/or bulk traps; and (3) fluorine's ineffectiveness in reducing NBTI in plasma-nitrided devices. We also observe the atomic-scale defects involved in NBTI in HfO2-based devices and find that short- and long-term stressing generates different defects and that these defects are different than those observed in the SiO2 and plasma-nitrided devices. Our results also suggest that the NBTI-induced defects in these devices are physically located in the interfacial layer (not at the interface).

Toward Understanding the Wide Distribution of Time Scales in Negative Bias Temperature Instability

Difficulties with evaluating Negative Bias Temperature Instability (NBTI) are linked to fast effects occurring at microsecond or possibly faster time scales. The wide distribution of time scales involved in NBTI relaxation suggests participation of some sort of dispersion in the underlying NBTI mechanism. A universal behavior of the relaxation is observed and used to benchmark several models incorporating dispersion. The impact of the boundary condition on the model based on dispersive transport is also briefly discussed. Furthermore, on-chip circuits are designed and fabricated to measure the effect of AC NBTI up to 2 GHz on individual devices. The results on both single pFET's and inverters indicate that AC NBTI is independent of the frequency in the entire 1 Hz - 2 GHz range. This suggests that any characteristic time scale of the NBTI mechanism must be below 1 ns.

NBTI Mechanism Based on Hole-Injection for Accurate Lifetime Prediction

The evaluation method of Negative Bias Temperature Instability (NBTI) based on hole-injection is proposed for accurate lifetime prediction of MOS devices. The acceleration parameters are most important for accurate lifetime prediction. Proposed acceleration parameter is not the applied voltage to the gate insulator film and the temperature but the injected hole injection quantity to the gate insulator film. The degradation mechanism in the excessive voltage and excessive temperature stresses are different from that in the operation conditions. In the relatively high hole-injection stress, the mechanism is also different from that in the operation conditions. It is considered that the difference is caused by the excess enhancement of the hole energy in the inversion layer. In the relatively low hole-injection stress, the degradation mechanism becomes the same as that in the operation conditions. The accurate lifetime prediction in MOSFET level and circuit level can be realized by hole-injection acceleration method.

Negative bias temperature instability mechanism: The role of molecular hydrogen

The role of dimerization of atomic hydrogen to give molecular hydrogen in determining negative bias temperature instability (NBTI) kinetics is explored analytically. The time dependency of NBTI involving molecular hydrogen was found to obey a power law with a slope of 1∕6, as opposed to the 1∕4 slope derived for a reaction involving atomic hydrogen. The implications of this dimerization reaction for voltage and temperature acceleration are also discussed. Simulation results validating these predictions are also described. The higher slopes typically reported for NBTI are shown to be an artifact of measurement, and experimental data supporting this lower time dependency is shown.

Negative Bias Temperature Instability Dependence on Dielectric Thickness and Nitrogen Concentration in Ultra-scaled HfSiON Dielectric/TiN Gate Stacks

Negative bias temperature instability (NBTI) of the HfSiON/TiN gate stack is investigated as a function of the dielectric thickness. It is shown that as the thickness of the HfSiON layer is reduced below 20 Å, the NBTI mechanism approaches the mechanism that induces H-reaction diffusion. Conversely, for thicker HfSiON dielectrics, a combination of H-reaction–diffusion and charge detrapping from the bulk HfSiON contribute to NBTI. MOS devives with plasma nitrided HfSiON (30 Å) with varying nitrogen (N) content as gate dielectric are studied with respect to NBTI and it is found that NBTI is dominated by electron detrapping from the bulk and the threshold voltage (VTH) shift reduces monotonically with increasing N content.

Evidence of two distinct degradation mechanisms from temperature dependence of negative bias stressing of the ultrathin gate p-MOSFET

A detailed investigation of the negative-bias temperature instability (NBTI) of the ultrathin nitrided gate p-MOSFET over a wide temperature range reveals two different activation energies, indicating the coexistence of two distinct degradation mechanisms. One mechanism is linked to the incorporation of nitrogen while the other is the classical mechanism responsible for the degradation of conventional SiO/sub 2/ gate devices. Eliminating the contribution of the former consistently yields an Arrhenius plot that matches excellently with that obtained through direct measurement of SiO/sub 2/ gate devices. This finding shows that heavy nitridation or, in the extreme case, the adoption of Si/sub 3/N/sub 4//SiO/sub x/ gate stack does not change the nature of the classical NBTI mechanism but introduces a new degradation mechanism of an order-of-magnitude lower activation energy, which dominates over typical operating temperature range. This new mechanism is related to the spontaneous trapping of positive charges at nitrogen-related precursor sites near the Si-SiO/sub 2/ interface.

Decoupled Plasma Nitridation 공정 적용을 통한 Negative Bias Temperature Instability 특성 개선

In this paper, the established model of NBTI (Negative Bias Temperature Instability) mechanism was reviewed. Based on this mechanism, then, the influence of nitrogen was discussed among other processes. A constant concentration of nitrogen exists inside <TEX>$SiO_2$</TEX> in order to prevent boron from diffusing and to increase dielectric constant. It was shown that NBTI improvement was achieved by controlling nitrogen profile. It was supposed that the existence of low activation energy of Si-N bonds at <TEX>$Si-SiO_2$</TEX> interface attributes the improvement by making hydrogen prevent interface traps. It was also shown that improvement of NBTI can be achieved by more effective control of nitrogen profile. It was supposed that the maximum control of nitrogen profile can be achieved by DPN (Decoupled Plasma Nitridation) process.

Negative bias temperature instability mechanisms in p-channel power VDMOSFETs

The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge. The results are analysed in terms of the mechanisms responsible for buildup of oxide charge and interface traps, and the model that explains experimental data is discussed in details.