Negative Bias Illumination Temperature Stress Research Articles

Origin of the High Density of Oxygen Vacancies at the Back Channel of Back-Channel-Etched a-InGaZnO Thin-Film Transistors.

This study reveals the pronounced density of oxygen vacancies (Vo) at the back channel of back-channel-etched (BCE) a-InGaZnO (a-IGZO) thin-film transistors (TFTs) results from the sputtered deposition rather than the wet etching process of the source/drain metal, and they are distributed within approximately 25 nm of the back surface. Furthermore, the existence and distribution depth of the high density of Vo defects are verified by means of XPS spectra analyses. Then, the mechanism through which the above Vo defects lead to the instability of BCE a-IGZO TFTs is elucidated. Lastly, it is demonstrated that the device instability under high-humidity conditions and negative bias temperature illumination stress can be effectively alleviated by etching and thus removing the surface layer of the back channel, which contains the high density of Vo defects. In addition, this etch method does not cause a significant deterioration in the uniformity of electrical characteristics and is quite convenient to implement in practical fabrication processes. Thus, a novel and effective solution to the device instability of BCE a-IGZO TFTs is provided.

Abnormal Positive Shift of Threshold Voltage in Praseodymium-Doped InZnO-TFTs Under Negative Bias Illumination Temperature Stress

Abnormal Positive Shift of Threshold Voltage in Praseodymium-Doped InZnO-TFTs Under Negative Bias Illumination Temperature Stress

30.3: Impact of Top Gate Insulator Deposition Temperature on Electrical Performance of Dual‐Gate a‐InZnO TFTs

The electrical characteristics and stability of dual‐gate amorphous InZnO thin film transistors (a‐IZO TFTs) with top gate insulators (TGIs) deposited under different conditions were investigated. It is found that the TFT with 150°C SiO2 as TGI has higher mobility, while TFT with 300°C SiO2 as TGI has lower off‐state leakage current and better stability under bias stress. Experimental results show that the TFT with stacked TGI deposited at 150°C first and then 300°C can combine the merit of the 150°C SiO2 and 300°C SiO2, achieving high saturation mobility (23.9 cm2/V·s), low off‐state leakage current (10‐14 ~10‐12 A) and also good stability under negative bias stress (NBS) and positive bias stress (PBS) of 3600 s @30 V, with only negative drift of 0.02 V and 0.15 V, respectively. Moreover, it also performs well under negative bias temperature illumination stress (NBTIS) and positive bias temperature illumination stress (PBTIS).

Electrical Reliability of Flexible Low-Temperature Polycrystalline Oxide Thin-Film Transistors Under Mechanical Stress

Electronic devices based on flexible displays have been developed for use in various applications. Upon bending such devices, the applied mechanical force deteriorates the reliability of the devices. Therefore, a high bending reliability that is influenced by tensile and compressive forces that vary depending on the bending radius of curvature must be secured to ensure a reliable device operation. In this study, we investigated the electrical characteristics of flexible low-temperature polycrystalline silicon (LTPS) and amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors (TFTs) on polyimide (PI) substrate and subsequently conducted reliability evaluation of the devices under mechanical stress by applying negative bias temperature illumination stress (NBTIS). The degradations in the electrical properties, such as threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> ) shift, OFF-state current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {off}}$ </tex-math></inline-formula> ), and subthreshold slope (SS), and reliability, increased, and the reliability worsened, as the tensile force increased under decreasing radius of curvature, whereas relatively low degradation occurred under compressive force. A tensile stress-induced increase in grain boundary state density in polycrystalline silicon (poly-Si) and oxygen vacancy in a-IGZO were verified by density of state (DOS) extraction; the cracks occurring due to tensile stress were optically analyzed; the external moisture penetration along the cracks further degrades the device characteristics. This study provides an analysis of device design for ensuring reliability under the application of mechanical stress, thereby contributing to the development of reliable flexible technology.

Enhanced stability and mobility of solution-processed oxide thin-film transistors with bilayer terbium-incorporated indium oxide channel

The trade-off between mobility and stability in oxide thin-film transistors (TFTs) hinders further advances of an active-matrix flat panel display. Herein, a solution-processed bilayer active channel is designed to improve the stability and mobility simultaneously. The optical bandgap and work function of Tb:In2O3 films are modulated by tuning the film thickness and Tb concentration of Tb-doped indium oxide (Tb:In2O3) films. Large conduction band offset is achieved in a Tb:In2O3 bilayer channel, which induces accumulation of abundant electrons at the interface. The mobility is significantly improved to 38.2 cm2/V s, and the photoinduced stability of bilayer Tb:In2O3 TFTs is improved with low threshold voltage shift of 0.26 and −0.38 V under negative-bias illumination stress and negative-bias temperature illumination stress, respectively.

Robust Mobility Enhancement and Comprehensive Reliability Evaluation for Amorphous InGaZnO TFT by Double Layers With Quantum Well Structures

Mobility enhancement is an important research topic for amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) since it is directly related to the device&#x2019;s performance. The double-layer a-IGZO channel with quantum well structure was proposed for mobility enhancement. However, the impact of such double layers with the quantum well structure on a-IGZO TFT reliabilities, i.e., positive bias temperature stress (PBTS) and negative bias temperature illumination stress (NBTIS), is still elusive. In this work, the mobility enhancement by double layers with quantum well structures is proven to be robust in mass production Gen 8.5 line. Then, the a-IGZO TFT under PBTS and NBTIS is investigated systematically. The variations of mobility <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>, subthreshold slope SS, and threshold voltage shift <inline-formula> <tex-math notation="LaTeX">${\Delta {V}_{\text {th}}}$ </tex-math></inline-formula> with PBTS and NBTIS stress time are evaluated and analyzed, respectively. It is shown that the double-layer a-IGZO channel with quantum well structure can sustain as good reliability performance as the reference single-layer device.

4‐2: Invited Paper: High Performance Top Gate Oxide TFT Technology for Large Area Flexible AMOLED Display

We have fabricated PI‐based IGZO TFTs with Cu electrode which exhibit excellent electrical properties and high mechanical reliabilities to meet the demand for large area flexible display. The IGZO TFTs show +0.26 V and −0.34 V of ΔVth under positive bias temperature stress and negative bias temperature illumination stress for 10 hours, respectively, and the Vth shift after laser lift‐off and bending test of 200,000 times are less than 0.08 V and 0.03 V, respectively. Finally, we successfully realize 16.9‐inch rollable OLED display with high performance top gate IGZO TFT, which can be rolled up to a radius of 20 mm.

Vertically Graded Oxygen Deficiency for Improving Electrical Characteristics and Stability of Indium Gallium Zinc Oxide Thin-Film Transistors.

We investigated a facile fabrication method, which is an insertion of a carrier-induced interlayer (CII) between the oxygen-rich a-IGZO channel and the gate insulator to improve the electrical characteristics and stability of amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs). The a-IGZO channel is deposited with additional oxygen gas flow during a-IGZO channel deposition to improve the stability of the a-IGZO TFTs. The CII is a less than 10 nm thick deposited thin film that acts to absorb the oxygen from the a-IGZO front channel through oxidation. Through oxidation of the CII, the oxygen concentration of the a-IGZO front channel is decreased compared to that of the oxygen-rich back channel, which forms a vertically graded oxygen deficiency (VGO) in the a-IGZO channel. Therefore, the electrical characteristics of the VGO TFTs are improved by increasing the carrier concentration of the front channel as the oxygen vacancy concentration in the front channel is increased through the oxidation of the CII. At the same time, the stability of the VGO TFTs is improved by maintaining a high oxygen concentration in the back channel even after oxidation of the CII. The field-effect mobility (μFET) of the VGO TFTs improved compared to that of the a-IGZO TFTs from 7.16 ± 0.6 to 12.0 ± 0.7 cm2/V·s. The threshold voltage (Vth) shifts under positive bias temperature stress and negative bias temperature illumination stress decreased from 6.00 to 2.95 V and -15.58 to -8.99 V, respectively.

P‐23: Enhancement in the Mobility and the Stability of Solution‐Processed Zinc‐Tin Oxide Thin‐Film Transistors Using Alkali Metal Superoxide

We have studied how to improve the mobility and stability of solution processed zinc‐tin oxide thin‐film transistors (ZTO TFTs) simultaneously using multifunctional potassium superoxide precursor. Potassium cations in the potassium superoxide precursor acts as a shallow donor in the ZTO thin film to improve the carrier concentration (electron), which allows the potassium‐doped ZTO TFT to exhibit high mobility. Then, the anion of the precursor exists as a superoxide radical, and it showed the effect of reducing the oxygen vacancy in the process of forming the oxide thin film Consequently, potassium‐doped ZTO TFT using potassium superoxide precursor exhibited improved mobility and stability, showing an increase in the mobility from 5.11 to 8.36 cm2/Vs and a decrease in the threshold voltage shift from 4.65 to 3.36 V under a negative bias temperature illumination stress test conducted over 5,000 sec..

39‐2: Development of Advanced LTPS TFT Technology for Low Power Consumption and Narrow Border LCDs

We have developed an advanced LTPS TFT technology in which top‐gate oxide TFTs are used in each pixel and CMOS LTPS TFTs are used in gate drivers and multiplexers in the peripheral circuits. Oxide TFTs have excellent Ids–Vgs characteristics with a small Vth shift under negative bias temperature illumination stress (NBTIS).

Extremely high-gain source-gated transistors

Despite being a fundamental electronic component for over 70 years, it is still possible to develop different transistor designs, including the addition of a diode-like Schottky source electrode to thin-film transistors. The discovery of a dependence of the source barrier height on the semiconductor thickness and derivation of an analytical theory allow us to propose a design rule to achieve extremely high voltage gain, one of the most important figures of merit for a transistor. Using an oxide semiconductor, an intrinsic gain of 29,000 was obtained, which is orders of magnitude higher than a conventional Si transistor. These same devices demonstrate almost total immunity to negative bias illumination temperature stress, the foremost bottleneck to using oxide semiconductors in major applications, such as display drivers. Furthermore, devices fabricated with channel lengths down to 360 nm display no obvious short-channel effects, another critical factor for high-density integrated circuits and display applications. Finally, although the channel material of conventional transistors must be a semiconductor, by demonstrating a high-performance transistor with a semimetal-like indium tin oxide channel, the range and versatility of materials have been significantly broadened.

Suppression of Light Influx Into the Channel Region of Photosensitive Thin-Film Transistors

Analysis on the light influx into a bottom-gate, etch-stopper structure thin-film transistor is presented. Reduction of the light influx by means of structural changes in the device can lead to a universal improvement in negative-bias temperature illumination stress instability of metal–oxide transistors. When the devices are illuminated by a fixed light source from below, the dominant light influx occurs in the channel-width direction, due to light reflections off the boundary between the passivation layer and the ambient. Wave propagation into the channel can be suppressed by using thinner dielectric layers or applying an overlying coating layer with a larger refractive index than that of the passivation dielectric material.

Stability of In-Ga-Zn-O metal-semiconductor field-effect-transistors under bias, illumination, and temperature stress

The stability of metal-semiconductor field-effect-transistors (MESFETs) with silver oxide Schottky gates on In-Ga-Zn-O (IGZO) channels, grown by mist chemical-vapor-deposition, was examined under different combinations of positive and negative bias, illumination, and temperature stress. These devices were remarkably stable, even under the most severe condition of negative-bias-illumination-temperature-stress (NBITS), where the threshold voltage shift after 10 h NBITS was only +0.12 V and was mainly attributed to a decrease in the carrier density of the channel. The stability of these IGZO MESFETs is associated with the use of a conducting Schottky gate that significantly reduces charge trapping at the gate-channel interface.

Improvement of Negative Bias Temperature Illumination Stability of Amorphous IGZO Thin-Film Transistors by Water Vapor-Assisted High-Pressure Oxygen Annealing

The effect of high-pressure annealing on the performance and negative bias temperature illumination stress (NBTIS)-induced instability of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) is investigated. IGZO TFTs that were annealed in a H2O vapor-assisted high-pressure O2 atmosphere exhibited significantly improved field-effect mobility and stability against NBTIS compared with those annealed in only high-pressure O2 or air. Annealing under high-pressure O2 in the presence of H2O vapor effectively reduces oxygen-related defects, which act as subgap states within the bandgap. This phenomenon affects band alignments, including the bandgap and conduction band offset [Δ(EC–EF)] of IGZO semiconductors, and is the basis for the improved performance and stability of the TFTs.

Solution-processed zinc-indium-tin oxide thin-film transistors for flat-panel displays

Highly uniform thin-films of zinc-indium-tin oxide (ZITO) semiconductors were formed using solution process with wet-annealing at a low temperature of 250 °C. The solution-processed ZITO thin-film transistors with a top-gate staggered structure were fabricated to exhibit field-effect mobility of 2.04 ± 0.28 cm2/Vs at saturation region, threshold voltage (Vth) of 2.15 ± 0.75 V, subthreshold slope of 0.27 ± 0.14 V/dec. and excellent reliability (ΔVth = −4.35 V) for negative bias temperature illumination stress. Based on the performance, a 10.1 in. full-color liquid crystal display was demonstrated by the optimized full photolithography process.

Defect reduction in photon-accelerated negative bias instability of InGaZnO thin-film transistors by high-pressure water vapor annealing

We investigated the effects of high-pressure water vapor annealing (WHPA) under negative bias temperature illumination stress and light incidence on amorphous InGaZnO thin-film transistors. WHPA could improve device reliability and reduce the hump occurrence. It was attributed to the effective reduction and passivation in oxygen vacancies under WHPA. By comparing the experimental and technology computer-aided design simulation, we could confirm that the low-density of deep-donor-like oxygen vacancy (Vo) states near the valance band maximum contributed to the reduction of photo-excited single ionized oxygen vacancies (Vo+) and double ionized oxygen vacancies (Vo2+) as shallow-donor states near the conduction band minimum.

Photoelectric heat effect induce instability on the negative bias temperature illumination stress for InGaZnO thin film transistors

This paper investigates the instability of negative bias temperature in the dark and the illumination stresses for the InGaZnO thin film transistors. During the negative bias temperature illumination stress, properties exhibit an obvious negative threshold voltage shift and a significant degradation of subthreshold swing. The photoelectric heat effect that combined the effects of electric field, illumination, and temperature induces the generation of dangling bonds in the interface, resulting in an apparent degradation. It is related to the presence of light energy. Finally, this work also employs the capacitance-voltage measurement and recovery behavior to further clarify the mechanism of degradation behaviors.

Full-Swing a-IGZO Inverter With a Depletion Load Using Negative Bias Instability Under Light Illumination

A high-performance amorphous indium-gallium-zinc-oxide thin-film transistor (TFT) inverter, which is composed of an enhancement mode driver and a depletion mode load, is implemented by selectively inducing the negative bias illumination temperature stress (NBITS) to the load TFT. Under NBITS, the transfer curve of the load TFT shows a parallel shift into the negative bias direction without a significant change in the subthreshold slope and recovers very slowly after terminating the NBITS even under harsh bias and temperature stress conditions. The proposed inverter shows much improved switching characteristics including higher voltage gain, wider swing range, and higher noise margins compared to the conventional inverter with an enhancement load.

SiO2완충층 두께에 따른 비정질 InGaZnO Pseudo-MOS Field Effect Transistor의 신뢰성 평가

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO -MOSFET) with a stacked (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a buffer layer. The roles of a buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and . Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin buffer layer which highlighted bias and light-induced hole trapping into the layer. As a results, the pseudo-MOS transistor with a 20-nm-thick buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility() of 12.3 , subthreshold slope (SS) of 148 mV/dec, trap density () of , negative bias illumination stress (NBIS) of 1.23 V, and negative bias temperature illumination stress (NBTIS) of 2.06 V.

Improvement in the negative bias illumination temperature stress instability of In–Ga–Zn–O thin film transistors using an Al2O3 buffer layer

AbstractThe negative bias illumination temperature stress (NBITS) instability of amorphous In–Ga–Zn–O thin film transistors with SiO2 and SiO2/Al2O3 gate dielectric layers was evaluated. The introduction of a thin Al2O3 layer between the channel and SiO2 layer decreased the threshold voltage shift (ΔVth) by ∼20% after a NBITS for 1000 s. The interfacial trap density of the two samples, estimated by conductance and off‐current measurements, were almost identical. The higher valence band offset (∼0.4 eV) at the Al2O3/In–Ga–Zn–O interface compared to the SiO2/In–Ga–Zn–O interface decreased the gate leakage current and bulk trapping of holes under illumination. (© 2011 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)