Negative Bias Stress Conditions Research Articles

High-Performance Tin Oxide Thin-Film Transistors Realized by Codoping and Their Application in Logic Circuits.

Tin oxide is a promising channel material, offering the advantages of being low-cost and environmentally friendly and having a wide band gap. However, despite the high electron mobility of SnO2 in bulk, the corresponding thin-film transistors (TFTs) generally exhibit moderate performance, hindering their widespread application. Herein, we proposed a codoping strategy to improve both the electrical property and the stability of SnO2 TFTs. A comparative analysis between doped and undoped SnO2 was conducted. It is observed that taking advantage of the difference in ionic radii between two dopants (indium and gallium) and the tin ions in the host lattice can effectively reduce impurity-induced strain. Additionally, we investigated the effect of codoping content on SnO2 TFTs. The optimal codoped SnO2 (TIGO) TFTs demonstrate high performance, featuring a field-effect mobility of 15.9 cm2/V·s, a threshold voltage of 0.2 V, a subthreshold swing of 0.5 V/decade, and an on-to-off current ratio of 2.2 × 107. Furthermore, the devices show high stability under both positive and negative bias stress conditions with a small threshold voltage shift of 1.8 and -1.2 V, respectively. Utilizing the TIGO TFTs, we successfully constructed a resistor-loaded unipolar inverter with a high gain of 10.76. This study highlights the potential of codoped SnO2 TFTs for advanced applications in electronic devices.

Enhancement of electrical performance in indium-zinc oxide thin-film transistors with HfO2/Al2O3 gate insulator deposited via low-temperature ALD

Several studies have been conducted on amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) with the aim of applying them to the next-generation low-power displays. To improve the electrical performance of conventional AOS TFTs, which are known for their poor switching characteristics, we fabricated indium-zin oxide (IZO) TFTs with HfO2/Al2O3 gate insulator deposited via low-temperature atomic layer deposition (ALD). We optimized the electrical performance of the fabricated TFTs by varying the thickness of the IZO channel and Al2O3 insulator, respectively. Compared to the samples with a thermally grown 150 nm thick SiO2 gate insulator, the samples with a 10 nm thick IZO channel and a 10/70 nm thick HfO2/Al2O3 gate insulator exhibited the subthreshold swing of 0.24 V/dec, saturation carrier mobility of 7.49 cm2/V∙s and on–off current ratio of 1.09 × 107, which were improved by more than 47 %, 64 % and 5 times, respectively. Also, the threshold voltage shift in positive and negative bias stress conditions were improved to + 0.90 and – 1.75 V, respectively.

Device feasibility and performance improvement methodologies for thin film transistors using In-Ga-Sn-O channels prepared by atomic-layer deposition

Thin film transistors (TFTs) using In-Ga-Sn-O (IGTO) active channel layers, which were prepared by atomic-layer deposition (ALD) techniques, were fabricated and characterized with exploring the optimum IGTO channel compositions and the process conditions for the formation of gate-stack structures. The introduction of an O3 oxidant was confirmed to secure a wider process window, which was explained by hydrogen incorporation from the protection layer/gate insulator stacked layers into the IGTO active channel. The cationic compositions of the IGTO thin films were controlled by subcyclic ratio design of each precursor. When the number of In-Ga precursor subcycles increased from 4 to 6, the Ga/Sn ratio increased from 3.5 to 4.0, leading to marked improvements in the VON characteristics of the fabricated IGTO TFTs. It was found from a comparative analysis on the device characteristics that the Ga/Sn ratio in the IGTO channel had a more dominant effect on the VON characteristics rather than the In/Ga ratio. The device using the channel with a cationic composition of 5.8:4.0:1.0 (In:Ga:Sn) exhibited the field-effect mobility of 19.1 cm2/V s, the subthreshold swing of 0.22 V/dec, and the threshold voltage (VTH) of 0.22 V, which corresponded to the best device characteristics among the fabricated devices. Furthermore, the VTH shifts were examined to be +0.4 and −0.4 V in positive and negative bias stress conditions, respectively, demonstrating excellent gate-bias stress stabilities. The obtained results suggest the device feasibility and fabrication process validity for the TFT applications using IGTO active channel layers prepared by ALD techniques.

Effect of interfacial InZnO conducting layer on electrical performance and bias stress stability of InAlZnO thin-film transistors

InAlZnO (IAZO) thin-film transistors (TFTs) containing an InZnO (IZO) conducting layer at the interface between the IAZO channel layer and the gate insulator layer were fabricated. The electrical characteristics and bias stress stability of the IAZO/IZO TFTs were examined as functions of the thickness of the interfacial IZO conducting layer (which was set as 1, 2, and 3 nm), and optimal performance of the TFTs was achieved when the thickness was 2 nm. The optimized IAZO/IZO TFT showed a saturation mobility of 52.6 cm2/V·s, which is superior to that of a pristine IAZO TFT (29.8 cm2/V·s). Furthermore, the threshold voltage shifts under positive and negative bias stress conditions simultaneously improved from +2.1 V to +1.0 V and from −1.1 V to −1.0 V, respectively. IAZO/IZO interfaces were analyzed by X-ray photoelectron spectroscopy to elucidate the cause of the improved device characteristics.

Surface depletion effect on negative bias stress instability of β-Ga2O3 (100) nanomembrane FETs

In this study, we report on negative bias stress (NBS) instability of bottom-gate β-Ga2O3 (100) field-effect transistors and the effect of surface states reduction by using an atomic layer deposited Al2O3 layer. The fabricated devices exhibit high electrical performance with a field-effect mobility of up to 71.6 cm2 V−1 · s−1 and a subthreshold slope of ∼0.2 V dec−1. However, the abnormal positive threshold voltage (VTH) shifts under NBS conditions were observed. These phenomena, resulting from the surface depletion effect due to surface defects including dangling bonds and surface states, were moderated and thus the positive VTH shift was altered into a conventional negative shift by using ALD-Al2O3 surface passivation. The results indicate that a high quality passivation layer is suggested to ensure β-Ga2O3 device performance and stability.

Flexible vertical-channel thin-film transistors using In-Ga-Zn-O active channel and polyimide spacer on poly(ethylene naphthalate) substrate

A flexible vertical-channel thin-film transistor (VTFT) with a channel length of 400 nm was fabricated on a poly(ethylene naphthalate) substrate. The vertical gate-stack composed of gate electrode/gate insulator/active channel was prepared by a conformal atomic layer deposition and a dry etching process of an organic polyimide spacer. The transfer characteristics of the fabricated flexible VTFT were well confirmed after the postannealing process at 200 °C, in which the on/off ratio was obtained to be 1.8 × 102. The threshold voltage shifts were estimated to be +6.1 and −4.5 V under the positive and negative bias-stress conditions for 104 s, respectively. The device characteristics showed no remarkable degradation when delaminating from the carrier glass substrate. Furthermore, there were no marked changes in transfer curves even when the device was bent with a radius of curvature of 10 mm. A suitable choice of spacer material, optimization of the dry etching process, and employment of ultra-thin flexible film substrate were suggested to appropriate solutions for enhancing the device performance of the proposed flexible VTFTs.

Effect of Ti Content on Physical Properties and Electrical Characteristics of High-k Yb2TiO5 Gate Dielectrics for InZnSnO Thin-Film Transistors

In this study, we investigated the impact of Ti content on structural properties and electrical characteristics of high-k Yb2TiO5 gate dielectrics for amorphous indium–zinc–tin-oxide (a-InZnSnO) thin-film transistor (TFT) devices. The Yb2TiO5 thin films with different Ti plasma conditions were integrated in metal-insulator-metal structures to check the electrical capabilities. The Yb2TiO5 a-InZnSnO TFT device fabricated at the 120 W condition exhibited excellent electrical characteristics in terms of a small threshold voltage (VTH) of 0.14 V, a low subthreshold swing of 202 mV/decade, a large field-effect mobility of 29.8 cm2/V-s, and a high Ion/Ioff current ratio of 2.7×108. In addition, the VTH stability of Yb2TiO5 a-InZnSnO TFT device was studied under both positive bias stress and negative bias stress conditions. The Yb2TiO5 thin film is a promising gate dielectric material for the fabrication of a-InZnSnO TFTs.

Structural and electrical properties of high-κ CeTixOy, ErTixOy and YbTixOy gate dielectrics for InZnSnO thin film transistors

The structural properties and electrical characteristics of high–κ CeTixOy, ErTixOy and YbTixOy gate dielectrics for indium–zinc–tin–oxide (IZTO) thin-film transistors (TFTs) were investigated in this paper. We employed X-ray diffraction to determine the material phase and crystallinity, atomic force microscopy to examine the surface morphology of the dielectric films, and X-ray photoelectron spectroscopy to analyze the chemical feature of three films. The IZTO TFT incorporating a YbTixOy gate dielectric exhibited better electrical characteristics, such as a low threshold voltage (VTH) of 0.17 V, a large field-effect mobility of 20.8 cm2/V-s, a high Ion/Ioff ratio of 3 × 108, and a low subthreshold slope of 108 mV/decade, in comparison with those of other dielectrics. This result suggests that the YbTixOy dielectric possesses a smoother surface as well as a lower oxygen vacancy (or defect). Moreover, the VTH stabilities of IZTO TFT devices were investigated for positive bias stress and negative bias stress conditions.

Achieving High Field-Effect Mobility Exceeding 50 cm<inline-formula> <tex-math notation="TeX">\(^{\mathrm {2}}\) </tex-math></inline-formula>/Vs in In-Zn-Sn-O Thin-Film Transistors

Bottom gate and etch stopper-type thin-film transistors (TFTs) with a channel layer of indium-zinc-tin oxide were fabricated. The resulting TFTs exhibited a high mobility exceeding 52 cm 2 /Vs, a low subthreshold gate swing of 0.2 V/decade, a threshold voltage of 0.1 V, and an I ON/OFF ratio of >2 × 10 8 . The stability of the oxide passivated device under the positive and negative bias stress conditions was superior to that of the nitride passivated device, which can be attributed to the lower trap density in the channel layer.

Electrical and Reliability Characteristics of High-$\kappa~{\rm HoTiO}_{3}~\alpha$-InGaZnO Thin-Film Transistors

In this letter, we investigated the electrical and reliability characteristics of high- κ HoTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> amorphous indium-gallium-zinc oxide ( α-IGZO) thin-film transistor (TFT) devices. The α-IGZO TFT device incorporating an HoTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> dielectric exhibited excellent electrical characteristics in terms of a low threshold voltage of 0.12 V, a high field-effect mobility of 21.4 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> , a small subthreshold swing of 160 mV/decade, and a high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> current ratio of 1.3 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> . These results are attributed to the incorporation of TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> into the Ho <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> film forming the smooth surface roughness and thus reducing the oxygen vacancies. Furthermore, the threshold voltage stability of HoTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> α-IGZO TFT was studied under both positive and negative bias stress conditions.

(1 1 0) and (1 0 0) Sidewall-oriented FinFETs: A performance and reliability investigation

The performance and reliability of (100) and (110) sidewall, silicon-on-insulator (SOI) FinFETs with a Hf-based gate dielectric were evaluated. Unlike the typical planar MOSFET mobility orientation dependence, (110) FinFET sidewalls do not impair electron mobility and result in good short channel performance compared to (100) FinFET sidewall devices. Hot carrier injection (HCI) degradation was also investigated with nMOS and pMOS high-κ FinFETs on both sidewall surface orientations. Impact ionization at the source, as well as at the traditional drain side, was found to enhance HCI degradation when gate voltage (Vg)=drain voltage (Vd). The degradation becomes more pronounced as the gate length decreases, with a negligible dependence on substrate orientation. However, the orientation dependence of negative bias temperature instability (NBTI) on FinFETs demonstrates that the (110) orientation is slightly worse than (100). The kinetics of ΔNIT(t) under negative bias stress conditions suggests the interface trap density (NIT) is generated by a mechanism similar to that in planar devices.

Gated Diode Investigation of Bias Temperature Instability in High- $\kappa$ FinFETs

Bias temperature instability (BTI) in FinFET transistors was investigated by charge-pumping (CP) and gated-diode measurements using n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> /p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> structures with the gate interface identical to that in SOI-FinFETs. The results show greatly improved sensitivity for gated diode measurements than for CP. The pre-stress interface trap density was found to be N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ≅ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> for SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /2 nm-HfSiON/TiN/polySi-capped gate stacks, which is about one decade larger than in planar devices. The kinetics of ΔN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> (t) under negative bias stress conditions (NBTI) suggests N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> is generated by Si-H bond breaking. The mechanism for interface trap generation under positive bias stress conditions (PBTI) requires further investigation.

Influence of Illumination on the Negative-Bias Stability of Transparent Hafnium–Indium–Zinc Oxide Thin-Film Transistors

The stability of transparent hafnium-indium-zinc oxide (HIZO) thin-film transistors (TFTs) was investigated under negative-bias stress conditions. TFTs that incorporate transparent electrode materials such as indium-tin oxide or indium-zinc oxide were studied, and the bias stress experiments showed that transparent TFTs undergo severe degradation (negative shift in threshold voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> ) with simultaneous exposure to white light, in comparison with the results obtained in dark. The time evolution of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> indicates that the deterioration under illumination occurs mainly by the trapping of photogenerated carriers near the HIZO/dielectric interface.