Near-threshold Logic Research Articles

A 746 nW ECG Processor ASIC Based on Ternary Neural Network.

This paper presents an ultra-low power electrocardiography (ECG) processor application-specific integrated circuit (ASIC) for the real-time detection of abnormal cardiac rhythms (ACRs). The proposed ECG processor can support wearable or implantable ECG devices for long-term health monitoring. It adopts a derivative-based patient adaptive threshold approach to detect the R peaks in the PQRST complex of ECG signals. Two tiny machine learning classifiers are used for the accurate classification of ACRs. A 3-layer feed-forward ternary neural network (TNN) is designed, which classifies the QRS complex's shape, followed by the adaptive decision logics (DL). The proposed processor requires only 1 KB on-chip memory to store the parameters and ECG data required by the classifiers. The ECG processor has been implemented based on fully-customized near-threshold logic cells using thick-gate transistors in 65-nm CMOS technology. The ASIC core occupies a die area of 1.08 mm2. The measured total power consumption is 746 nW, with 0.8 V power supply at 2.5 kHz real-time operating clock. It can detect 13 abnormal cardiac rhythms with a sensitivity and specificity of 99.10% and 99.5%. The number of detectable ACR types far exceeds the other low power designs in the literature.

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes

Extending double-gate FinFET scaling to sub-10nm technology regime requires device-engineering techniques for countering the rise of direct source to drain tunneling (DSDT), edge direct tunneling (EDT) and short channel effects (SCE) that degrade FinFET I-V characteristics. Symmetric underlap is effective for eliminating EDT, diminishing DSDT, and lowering the fringe component of gate capacitance. However, excessive symmetric underlap also lowers the on-current, which is mainly due to thermionic emission. In this work, it is demonstrated that at sub-10nm node, asymmetric underlapped FinFETs with slightly longer underlap toward drain side than source side are superior to symmetric underlapped FinFETs due to further improvement in I on /I off and reduction in gate-to-drain capacitance. Using quantum mechanical device simulations, FinFETs with various degrees of underlap have been analyzed for improvement in I-V characteristics. A FinFET model for circuit simulations has been constructed that captures the major sub-10nm leakage components, namely, thermionic emission, DSDT, EDT, direct gate oxide tunneling and its associated components. By simulating a 10-stage NAND circuit and a LEON3 processor with interconnect parasitics using these devices, it is shown that asymmetric underlap instead of symmetric underlap in sub-10nm FinFETs can offer lower energy consumption with improved performance for near-threshold logic and higher energy-efficiency for super-threshold logic operation.

(Invited) Heterogeneous Nano- to Wide-Scale Co-Integration of Beyond-Si and Si CMOS Devices to Enhance Future Electronics

With the growing need to pack more functionality into a smaller form-factor while providing significant power-performance benefits, future electronics will need fairly disruptive solutions to overcome the mounting limits of Si CMOS scaling. At the core of the hardware innovations will be new process technologies that not allow for more power-efficient CMOS transistors but also specialized devices to enable new on-chip functionality, E.g. Near-Threshold Logic, High-speed I/O, Optoelectronics, etc. Heterogeneous integration ranging from TSV-based chip stacking to monolithic 3-D integration are active areas of R&D with the common aim to enhanced chip density and functionality. In order to leverage the dense Si CMOS logic and memory fabric, most, if not all approaches also require the integration to be compatible, to different extent, with large-scale 300mm CMOS processes, and potentially >300mm wafers, in the future. At the finest grain, co-integration of different beyond-Si crystalline material (E.g. III-V, Ge, SiGe, etc.) with Si require significant innovations in defect, stress, and process thermal-budget management. With the maturation of epitaxy process technology, the ability to combine materials of large lattice mismatch is becoming possible with lowering defectivity. Through defect engineering, we will soon have options to integrate IIIV and Ge-based material on Si at different scale, from global wafer level to fine-grain local levels of the order of circuits and devices (Figs. 1 and 2). This opens up possibilities to integrate heterogeneous devices that leverage the unique properties offered by epitaxial combination of materials. Besides high-channel carrier mobility, integrating compound semiconductors heterostructures into multi-gated nano-devices like FinFETs (Fig. 3) combines Fin structural confinement with quantum well confinement enhancing the electrostatics of FinFET structures (Fig. 4). Due to the intrinsic lower band-gap of high-mobility channels (InGaAs, Ge, etc.), which leads to increase band-to-band tunneling leakage, there may be a need to co-integrate wider band-gap devices to address the low-leakage components (Eg. Low-standby leakage circuits, High-density SRAM, etc.) at the system level. Hence, a method of integrating different channel materials on the same die is called for. With the flexibility to direct heteroepitaxy on Si, the possibility to build hybrid systems of novel devices and MOSFETs become real. For example for an ultra-low Vdd Tunnel-FET (for ultra-low Vdd logic) process may be achieved by a grow-and-etch approach or by an epitaxy replacement process on Si. For example, with source replacement, asymmetric vertical device structures can be integrated in the form of TFETs (Fig. 7). Polarity and performance of TFETs can be selectively modulated by the source material replacement process (Fig. 8). The mix and match of different devices and circuits will need careful considerations of circuit layouts, which bring new parasitic factors (Fig. 9) which will need to be overcome. Extending beyond integration of 3-D semiconductors, further heterogeneity with emerging materials like 2-D Transition metal dichalcogenides crystals and spintronics offer even richer possibilities for future on-a-chip electronic systems. This paper will look into the materials, process, device and circuit considerations to enable monolithically-integrated heterogeneous materials, devices, and systems. Figure 1

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization

Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements

This study aims to understand the potential of bulk FinFET technology from the perspective of sub- and near-threshold logic circuits down to 100-mV bias voltage. Measurements are performed on bulk FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and with a high- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$k$</tex></formula> /metal-gate stack having an equivalent thickness in inversion of 1.6 nm. For comparison purposes, measurements are also performed on bulk planar FETs with the same channel length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. planar devices. After adjusting for the different threshold voltages, FinFETs exhibit perfect balance between n- and p-FETs at any applied bias in the sub- and near-threshold regimes. As a consequence, FinFET logic circuits have significantly improved voltage scalability from the perspective of dc robustness and of performance/energy.

0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS

In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.