Near-ideal Subthreshold Swing Research Articles

Near-Ideal Subthreshold Swing in Scaled 2D Transistors: The Critical Role of Monolayer hBN Passivation

Near-Ideal Subthreshold Swing in Scaled 2D Transistors: The Critical Role of Monolayer hBN Passivation

Performance potential of transistors based on tellurium nanowire arrays: A quantum transport study

Low-dimensional nanomaterials provide promising material platforms for aggressively scaled transistor technologies. We assess the performance potential of transistors based on an array of Tellurium nanowires (TNWs), by parameterizing a machine-learning (ML) tight-binding model with quantum transport device simulations. It has been shown that a transistor based on a parallel array of carbon nanotubes (CNTs) can have excellent on-state performance, but the small bandgap limits the transistor scalability and off-state performance. Our results indicate that compared to the CNT array FETs, the TNW array FETs have significantly suppressed ambipolar transport and improved subthreshold characteristics. The TNW array FET has the potential to achieve a near-ideal subthreshold swing (SS) close to 60 mV/dec, a very large on–off ratio (>109), and low source-drain leakage current at a 10 nm-scale channel length, due to its excellent gate electrostatics with a gate-all-around (GAA) structure, larger band gap and reduced quantum–mechanical tunneling. The TNW array FET also shows excellent scalability with a SS below 100 mV/dec when the channel length is further scaled down to 5 nm. Its larger bandgap and heavier effective mass significantly reduce quantum tunneling. This mechanism contributes to improved subthreshold and lower leakage but also highlights the need to develop low Schottky barrier contacts for TNWs.

Silicon–van der Waals heterointegration for CMOS-compatible logic-in-memory design

Silicon CMOS-based computing-in-memory encounters design and power challenges, especially in logic-in-memory scenarios requiring nonvolatility and reconfigurability. Here, we report a universal design for nonvolatile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By leveraging the photo-controlled charge trapping/detrapping process and the partially top-gated energy band landscape, the van der Waals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Precise polarity tunability, logic nonvolatility, robustness against high temperature (at 85°C), and near-ideal subthreshold swing (80 mV dec −1 ) can be done. A comprehensive investigation of dynamic charge fluctuations provides a holistic understanding of the origins of nonvolatile reconfigurability (a trap level of 10 13 cm −2 eV −1 ). Furthermore, we cascade such nonvolatile reconfigurable units into a monolithic circuit layer to demonstrate logic-in-memory computing possibilities, such as high-gain (65 at V dd = 0.5 V) logic gates. This work provides an innovative 3D heterointegration prototype for future computing-in-memory hardware.

In Situ Measurement of Effective Gate Bias Voltage in Ionic Liquid-Gated Organic Field-Effect Transistors: Exploring Intrinsic Performance and Trap Density of States.

Electric double layer (EDL)-mediated transistors with ionic liquid (IL) gating have garnered substantial interest due to their exceptional properties, such as high transconductance and low-voltage operation, positioning them as promising candidates for organic electronics. In this study, we present an in situ measurement of effective gate bias voltage (VGS,eff) in IL-gated organic field-effect transistors (IL-OFETs) using a modified current-voltage measurement configuration. The results reveal a significant deviation between VGS,eff and the applied gate bias (VGS,app), indicating that the EDL at the gate/IL interface screens the applied voltage. It is observed that the screening effect varies depending on the specific cation and anion present in the IL. The evaluation of VGS,eff plays a pivotal role in understanding the intrinsic behavior of IL-OFETs and addresses the challenges associated with accurate performance assessment. Inherently, IL-OFETs demonstrate high transconductance, achieving values of approximately 9 mS while operating at a low threshold voltage of around 0.55 V. Through the acquisition of VGS,eff, we have successfully addressed the limitations impeding the numerical estimation of the trap density of states (trap DOS) in IL-OFETs. Remarkably, our calculations reveal an exceptionally low density of deep traps, which serves as a crucial factor contributing to the near-ideal subthreshold swing (61-68 mV dec-1) observed in IL-OFETs. Further investigations unveil the neutral electrical nature of the IL bulk during OFET operation, confirming the hypothesis that the applied gate bias voltage in electrolyte-gated OFETs drops across the EDLs formed at the interfaces. The impedance spectroscopic (IS) analysis confirms the low contact resistance (≈1 Ω·m) of IL-OFETs calculated using the transition voltage method. The IS analysis also reveals the low-transmissive nature of the IL/organic semiconductor interface. The knowledge gained from this study holds significant implications for realizing high-performance electrolyte-gated OFETs in various applications including digital electronics, energy storage, and sensing. By unraveling the factors influencing the device performance, such as VGS,eff and trap DOS, this research contributes to the advancement of organic electronics and paves the way for future developments in the field.

Ti3 C2 Tx MXene van der Waals gate contact for GaN high electron mobility transistors.

Gate controllability is a key factor that determines the performance of GaN high electron mobility transistors (HEMTs). However, at traditional metal-GaN interface, direct chemical interaction between metal and GaN can result in fixed charges and traps, which can significantly deteriorate the gate controllability. In this study, Ti3 C2 Tx MXene films were integrated into GaN HEMTs as the gate contact, wherein van der Waals heterojunctions were formed between MXene films and GaN without direct chemical bonding. The GaN HEMTs with enhanced gate controllability exhibited an extremely low off-state current (IOFF ) of 10-7 mA/mm, a record high ION /IOFF current ratio of ∼1013 (which is six orders of magnitude higher than conventional Ni/Au contact), a high off-state drain breakdown voltage of 1085V, and a near-ideal subthreshold swing of 61mV/dec. This work shows the great potential of MXene films as gate electrodes in wide-bandgap semiconductor devices. This article is protected by copyright. All rights reserved.

Near-Ideal Top-Gate Controllability of InGaZnO Thin-Film Transistors by Suppressing Interface Defects with an Ultrathin Atomic Layer Deposited Gate Insulator.

An ultrathin atomic-layer-deposited (ALD) AlOx gate insulator (GI) was implemented for self-aligned top-gate (SATG) amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Although the 4.0-nm thick AlOx exhibited ideal insulating properties, the interaction between ALD AlOx and predeposited a-IGZO caused a relatively defective interface, thus giving rise to hysteresis and bias stress instabilities. As analyzed using high-resolution transmission electron microscopy, X-ray photoelectron spectroscopy, and the Hall measurement, the chemical reaction between the ALD precursor and a-IGZO is revealed. This was effectively prevented by preoxidizing a-IGZO with nitrous oxide (N2O) plasma. With 4 nm-AlOx GI and low-defect interfaces, high performance and stability were simultaneously achieved on SATG a-IGZO TFTs, including a near-ideal record-low subthreshold swing of 60.8 mV/dec, a low operation voltage below 0.4 V, a moderate mobility of 13.3 cm2/V·s, a low off-current below 10-13 A, a large on/off ratio over 109, and negligible threshold-voltage shifts less than 0.04 V against various bias-temperature stresses. This work clarifies the vital interfacial reaction between top-gate high-k dielectrics and amorphous oxide semiconductors (AOSs) and further provides a feasible way to remove this obstacle to downscaling SATG AOS TFTs.

3 nm Channel MoS2 Transistors by Electromigration of Metal Interconnection

Further scaling down the feature size of transistors is central for the development of next-generation electronic devices. However, fabrication of transistors with channel lengths down to 5 nm has been challenging due to lithography limit and short channel effects (SCEs). Here, we demonstrate an MoS2-based device with the shortest 3 nm channel length among global back-gated transistors by feedback-controlled electromigration of metal interconnection. The Si/SiO2-back-gated model device shows on/off ratios of up to 2 × 105 and exhibits a field-effect mobility of up to 33.5 cm2 V–1 s–1, which is, to the best of our knowledge, the highest value in the as-yet-reported same-type transistors with a sub-10 nm channel length. This good immunity of the device to SCEs is also corroborated by the COMSOL Multiphysics simulation. After replacing the thicker physical gate SiO2 dielectric and Si electrode with the 2D hexagonal boron nitride (h-BN) and graphene monolayer, respectively, for better gate control, the field-effect mobility is pushed to 51.2 cm2 V–1 s–1 and displays excellent switching characteristics with near-ideal subthreshold swing of 67 mV dec–1 and drain-induced barrier lowering as low as 0.378 V V–1. This work can promote further transistor downscaling and extend Moore’s law.

Near-Ideal Subthreshold Swing in InAlN/GaN Schottky Gate High Electron Mobility Transistor Using Carbon-Doped GaN Buffer

This work presents a comparative study of the subthreshold swing (SS) in InAlN/GaN-based high electron mobility transistor (HEMT), with and without carbon doping in the buffer layer. It is observed that devices with carbon-doped (C-doped) buffer exhibit near-ideal SS of close to 60-mV/decade over a wide range of drain voltage for both up and downsweep. The C-doped buffer layer reduces the OFF-state drain leakage current and increases the drain current ON/OFF ratio. TCAD simulation of the vertical electric field under the gate shows that the sample with a C-doped buffer layer has a much lower value of the peak electric field at the drain side edge of the gate, resulting in lower reverse-biased gate leakage current and smaller SS compared to that of the undoped buffer. Moreover, the junction capacitance at the interface of the unintentionally doped GaN (UID:GAN) and the C-doped buffer layer, in series with the depletion capacitance, reduces the overall capacitance, which further improves the SS in the C-doped wafer.

Improved Electrical Properties of Top-Gate MoS2Transistor With NH3-Plasma Treated HfO2as Gate Dielectric

The effects of NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treating HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric on electrical characteristics of top-gate (TG) MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs are investigated. The experimental results show that the increase of off-state current after growing HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> top-gate dielectric can be considerably decreased by NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treating HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , because the N incorporation from the NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treatment can effectively eliminate the oxygen vacancies and reduce the positive oxide charges in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The fabricated TG MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs with the NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as gate dielectric achieve excellent electrical performances: high on-off ratio of 2.1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> , high carrier mobility of 78~87 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs and near-ideal subthreshold swing of 72mV/dec. Therefore, the NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as gate dielectric is highly beneficial for fabricating high-performance TG MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs.

High-performance self-powered photodetector based on Bi2O2Se nanosheets

2D layered material Bi2O2Se nanosheets, due to its high carrier mobility, near-ideal subthreshold swing, and high air-stability, which have shown great potential for applications in high-performance field-effect transistors and photodetector. Here, we have been successfully synthesized Bi2O2Se nanosheets via a facile one-step hydrothermal method. The Bi2O2Se nanosheets were characterized by scanning electron microscopy (SEM), Raman spectra and X-ray diffraction (XRD) patterns, which confirm an excellent crystallized of Bi2O2Se nanosheets. The as-prepared Bi2O2Se nanosheets were used to fabricate electrodes for a self-powered photodetector and exhibit preferable photoresponse activity. At 0 V, the photoeletrochemical (PEC) tests demonstrate that the responsivity and the response time of Bi2O2Se nanosheets can reach up to 20 μA W−1 and 0.12 s. Furthermore, the time stability and cycle stability also were measured. After a long time of testing, the photocurrent of Bi2O2Se nanosheets remained around 300 nA, and after processing 100 and 200 cycles, the photocurrent exhibits slight distinction. These findings indicate that Bi2O2Se nanosheets have great prospects for future applications in self-powered photodetector devices.

A high-performance MoS2 synaptic device with floating gate engineering for neuromorphic computing

As one of the most important members of the two dimensional chalcogenide family, molybdenum disulphide (MoS2) has played a fundamental role in the advancement of low dimensional electronic, optoelectronic and piezoelectric designs. Here, we demonstrate a new approach to solid state synaptic transistors using two dimensional MoS2 floating gate memories. By using an extended floating gate architecture which allows the device to be operated at near-ideal subthreshold swing of 77 mV/decade over four decades of drain current, we have realised a charge tunneling based synaptic memory with performance comparable to the state of the art in neuromorphic designs. The device successfully demonstrates various features of a biological synapse, including pulsed potentiation and relaxation of channel conductance, as well as spike time dependent plasticity (STDP). Our device returns excellent energy efficiency figures and provides a robust platform based on ultrathin two dimensional nanosheets for future neuromorphic applications.

Near-ideal subthreshold swing MoS2 back-gate transistors with an optimized ultrathin HfO2 dielectric layer

In this paper, a near-ideal subthreshold swing MoS2 back-gate transistor with an optimized ultrathin HfO2 dielectric layer is reported with detailed physical and electrical characteristics analyses. Ultrathin (10 nm) HfO2 films created by atomic-layer deposition (ALD) at a low temperature with rapid-thermal annealing (RTA) at different temperatures from 200 °C to 800 °C have a great effect on the electrical characteristics, such as the subthreshold swing (SS), on-to-off current (ION/IOFF) ratio, etc, of the MoS2 devices. Physical examinations are performed, including x-ray diffraction, atomic force microscopy, and electrical experiments of metal-oxide-semiconductor capacitance-voltage. The results demonstrate a strong correlation between the HfO2 dielectric RTA temperature and the film characteristics, such as film density, crystallization degree, grain size and surface states, inducing a variation in the electrical parameters, such as the leakage, Dit, equivalent oxide thickness, SS, and ION, as well as ION/IOFF of the MoS2 field effect transistors with the same channel materials and fabrication methods. With a balance between the crystallization degree and the surface state, the ultrathin (10 nm) HfO2 gate dielectric RTA at 500 °C is demonstrated to have the best performance with a field effect mobility of 40 cm2 V−1 s−1 and the lowest SS of 77.6 mV−1 decade, which are superior to those of the control samples at other temperatures. The excellent transistor results with an optimized industry-based HfO2 ALD and RTA process provide a promising approach for MoS2 applications into the scaling of the nanoscale CMOS process.

Thick Layered Semiconductor Devices with Water Top-Gates: High On–Off Ratio Field-Effect Transistors and Aqueous Sensors

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore deionized (DI) water as a solution top-gate for field-effect switching of layered semiconductors including SnS2, MoS2, and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on-off current ratios, near-ideal subthreshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels, where such control is difficult to realize with conventional back gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics

High quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al2O3 dielectric demonstrate a near-ideal subthreshold swing of ∼60 mV/dec and a high field effect mobility of 100 cm2/V·s.

Near-zero hysteresis and near-ideal subthreshold swing in h-BN encapsulated single-layer MoS2 field-effect transistors

While two-dimensional (2D) van der Waals (vdW) layered materials are promising channel materials for wearable electronics and energy-efficient field-effect transistors (FETs), large hysteresis and large subthreshold swing induced by either dangling bonds at gate oxide dielectrics and/or trap molecules in bubbles at vdW interface are a serious drawback, hampering implementation of the 2D-material based FETs in real electronics. Here, we report a monolayer MoS2 FET with near-zero hysteresis reaching 0.15% of the sweeping range of the gate bias, a record-value observed so far in 2D FETs. This was realized by squeezing the MoS2 channel between top h-BN layer and bottom h-BN gate dielectrics and further removing the trap molecules in bubbles at the vdW interfaces via post-annealing. By segregating the bubbles out to the edge of the channel, we also obtain excellent switching characteristics with a minimum subthreshold swing of 63 mV/dec, an average subthreshold slope of 69 mV/dec for a current range of four orders of magnitude at room temperature, and a high on/off current ratio of 108 at a small operating voltage (<1 V). Such a near-zero hysteresis and a near-ideal subthreshold limit originate from the reduced trap density of ~5.2 × 109 cm−2 eV−1, a thousand times smaller than previously reported values.

PtSe2 Field-Effect Transistors: New Opportunities for Electronic Devices

PtSe2, a new family of transition metal dichalcogenides, has been explored for electronic device applications using density functional theory and non-equilibrium Green’s function within the third nearest neighbor tight-binding approximation. Interestingly, despite its small effective mass ( ${m}_{e}^{\ast } $ as low as $0.21{\mathrm {m}}_{\text {0}}$ ; ${\mathrm {m}}_{\text {0}}$ being electron rest mass), PtSe2 has large density of states due to its unique six-valley conduction band within the first Brillouin zone, unlike MoX2 family. This has direct impacts on the device characteristics of PtSe2 field-effect transistors, resulting in superior on-state performance (30% higher on current and transconductance) as compared with the MoSe2 counterpart. Our simulation shows that the PtSe2 device with a channel longer than 15 nm exhibits near-ideal subthreshold swing, and sub-100 mV/V of drain-induced barrier lowering can be achieved with an aggressively scaled gate oxide, demonstrating new opportunities for electronic devices with novel PtSe2.

Electrical characterization of top-gated molybdenum disulfide field-effect-transistors with high-k dielectrics

High quality HfO2 and Al2O3 substrates are fabricated in order to study their impact on top-gate MoS2 transistors. Compared with top-gate MoS2 FETs on a SiO2 substrate, the field effect mobility decreased for devices on HfO2 substrates but substantially increased for devices on Al2O3 substrates, possibly due to substrate surface roughness. A forming gas anneal is found to enhance device performance due to a reduction in charge trap density of the high-k substrates. The major improvements in device performance are ascribed to the forming gas anneal. Top-gate devices built upon Al2O3 substrates exhibit a near-ideal subthreshold swing (SS) of ~69mV/dec and a ~10× increase in field effect mobility, indicating a positive influence on top-gate device performance even without any backside bias.

High electron mobility and quantum oscillations in non-encapsulated ultrathin semiconducting Bi2O2Se.

High-mobility semiconducting ultrathin films form the basis of modern electronics, and may lead to the scalable fabrication of highly performing devices. Because the ultrathin limit cannot be reached for traditional semiconductors, identifying new two-dimensional materials with both high carrier mobility and a large electronic bandgap is a pivotal goal of fundamental research. However, air-stable ultrathin semiconducting materials with superior performances remain elusive at present. Here, we report ultrathin films of non-encapsulated layered Bi2O2Se, grown by chemical vapour deposition, which demonstrate excellent air stability and high-mobility semiconducting behaviour. We observe bandgap values of ∼0.8 eV, which are strongly dependent on the film thickness due to quantum-confinement effects. An ultrahigh Hall mobility value of >20,000 cm2 V-1 s-1 is measured in as-grown Bi2O2Se nanoflakes at low temperatures. This value is comparable to what is observed in graphene grown by chemical vapour deposition and at the LaAlO3-SrTiO3 interface, making the detection of Shubnikov-de Haas quantum oscillations possible. Top-gated field-effect transistors based on Bi2O2Se crystals down to the bilayer limit exhibit high Hall mobility values (up to 450 cm2 V-1 s-1), large current on/off ratios (>106) and near-ideal subthreshold swing values (∼65 mV dec-1) at room temperature. Our results make Bi2O2Se a promising candidate for future high-speed and low-power electronic applications.

Tin disulfide-an emerging layered metal dichalcogenide semiconductor: materials properties and device characteristics.

Layered metal dichalcogenides have attracted significant interest as a family of single- and few-layer materials that show new physics and are of interest for device applications. Here, we report a comprehensive characterization of the properties of tin disulfide (SnS2), an emerging semiconducting metal dichalcogenide, down to the monolayer limit. Using flakes exfoliated from layered bulk crystals, we establish the characteristics of single- and few-layer SnS2 in optical and atomic force microscopy, Raman spectroscopy and transmission electron microscopy. Band structure measurements in conjunction with ab initio calculations and photoluminescence spectroscopy show that SnS2 is an indirect bandgap semiconductor over the entire thickness range from bulk to single-layer. Field effect transport in SnS2 supported by SiO2/Si suggests predominant scattering by centers at the support interface. Ultrathin transistors show on-off current ratios >10(6), as well as carrier mobilities up to 230 cm(2)/(V s), minimal hysteresis, and near-ideal subthreshold swing for devices screened by a high-k (deionized water) top gate. SnS2 transistors are efficient photodetectors but, similar to other metal dichalcogenides, show a relatively slow response to pulsed irradiation, likely due to adsorbate-induced long-lived extrinsic trap states.

(Invited) Flexible GHz Frequency and Low-Power Nanoelectronics Based on 2D Nanomaterials

In this paper, substantial recent progress on graphene and transitional metal dichalcogenides on flexible substrates and the resulting high-performance electronic properties will be highlighted. Nearly defect-free monolayer graphene can now be synthesized by CVD at large-scales with material quality comparable to ex-foliated natural flakes. Fabricated transistor devices from CVD graphene on polyimide now readily afford transit frequencies around 25GHz, sufficient to realize radio-frequency circuits. Exfoliated dichalcogenides offer a route for basic experimental studies on soft substrates. MoS2 transistors on polyimide offer electronic performance comparable to devices on hard silicon substrates, including high on-off current ratio, near-ideal subthreshold swing, and current saturation. Device failure at high strains are either due to dielectric cracks or buckle delamination.