Nature Of Nanowires Research Articles

MECHANICAL PROPERTIES OF RNA NANOWIRES

RNA is a polymeric genetic bio-molecule found in all human beings. It is the main genetic material in many viruses. In this paper we test the mechanical properties of RNA NWs. We will find Youngs Modulus of RNA Nanowires (NWs) as a function of diameter with taking equilibrium strain, Poissons ratio and surface stress in consideration. As previously no study has been published regarding Youngs Modulus of RNA we take a theoretical approach towards it. We will predict the behavior of RNA NWs and see the resemblance to either semiconducting or metallic nature of NWs. This study extrapolates key factors in modelling RNA NWs for the creation of nanowires based aptasensors, genetics and other related applications.

Effect Of Phases On The Energetics Of Pristine InP Nanowires: An Ab-initio Approach

We have investigated the electronic and structural properties of pristine Zinc-blende type InP nanowires (NWs) by using ab-initio approach. We have considered the effect of phases by taking NWs of 7 A radii in three phases viz. (100), (110), (111). It is revealed that the electronic properties of NWs are highly affected by the wire phases. NW in (100) phase is found to be semiconducting with an indirect band gap of 0.71 eV whereas it becomes semi-metallic and metallic in other two phases. Thus, the nature of nanowires is observed as a function of NW phases. Further, energetic feasibility of InP NWs strongly dependent on their growth phase. Copyright © 2016 VBRI Press.

Investigation of gate-all-around silicon nanowire transistors for ultimately scaled CMOS technology from top-down approach

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the key issues regarding SNWTs from the top-down approach including process integration, carrier transport, and fluctuation and variability in these unique one-dimensional stronglyconfined nanowire devices. A new process integration scheme for SNWTs is discussed, which features a fully-Si-bulk substrate, an epi-free process, a self-aligned structure and a large source/drain fan-out. The physical characteristics of the fabricated devices with 10-nm-diameter nanowires are further investigated. The carrier transport performance in SNWTs is experimentally estimated, with a modified extraction methodology which takes into account the impact of temperature dependence of parasitic source resistance. SNWTs with sub-40-nm gate lengths exhibit high ballistic efficiency at room temperature, indicating great potential for SNWTs as an alternative device structure for near-ballistic transport. For heat transfer in SNWTs, the self-heating effect is also characterized. However, due to the one-dimensional (1-D) nature of nanowires and increased phonon-boundary scattering in the GAA structure, the self-heating effect in SNWTs based on the bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus, special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally studied in detail. The results of extracted variation sources indicate that, with suppressed random dopant fluctuations in the intrinsic channel, variations in radius and metal-gate work function of SNWTs dominate both the threshold voltage and on-current fluctuations. Comparing with conventional planar MOS devices, SNWT based SRAM cells exhibit better stability due to the superior electrostatic control in SNWTs.

Dynamic fatigue studies of ZnO nanowires by in‐situ transmission electron microscopy

AbstractThe fatigue behavior of ceramic ZnO nanowires (NWs) has been investigated under resonance cyclic loading conditions using in‐situ transmission electron microscopy (TEM). After mechanical deformation at the resonance frequency at a vibration angle of 5.2° for 35 billion cycles, no failure or any defect generations have been found. We believe that the dislocation‐free nature of NWs and the large surface‐to‐volume ratio contribute to the NWs' ability to undergo deformation without fatigue or fracture, proving their durability and toughness for nanogenerators and nanopiezotronics.magnified image(© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Fabrication and Transport Behavior Investigation of Gate-All-Around Silicon Nanowire Transistor from Top-Down Approach

Gate-all-around silicon nanowire transistor (SNWT) can be considered as the potential candidate for highly scaled devices. This paper mainly discusses a new process integration scheme, which features bulk substrate based, epi-free integration, self-aligned structure and large source/drain fan-out. The characteristics of the fabricated device with 10nm diameter nanowire were investigated. The transport behavior of the SNWTs is experimentally estimated, with a modified experimental extraction methodology for SNWTs given, which takes into account the impact of temperature dependence of parasitic resistance. The sub-40nm SNWTs exhibit high ballistic efficiency at room temperature. Self-heating effect is also experimentally characterized and due to the 1-D nature of nanowire and increased phonon-boundary scattering in GAA structure, the self-heating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected.

Investigation on Self-Heating Effect in Gate-All-Around Silicon Nanowire MOSFETs From Top-Down Approach

The self-heating effect is becoming a critical concern for nanoscaled devices with low dimensions. In this letter, the self-heating effect is experimentally investigated in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) fabricated from the CMOS-compatible top-down approach. With the multifinger and multiwire test structure, the impact of the self-heating effect is successfully characterized. The results indicate that even if the SNWT is fabricated on the bulk silicon substrate, the impact of the self-heating effect is comparable or even a little bit worse than that in SOI devices, probably due to the 1-D nature of nanowire and increased phonon-boundary scattering in the GAA architecture.

Quo Vadis Nanoelectronics?

AbstractSemiconductor devices continue to be downscaled on a regular basis as technology provides the ability to make smaller dimensions via improved lithography, a process which is known as Moore's Law. However, the driving force for the continued increase in number of devices on a chip is not this reduction in size, but the ability to put more functions on a chip with the same cost per unit area of Si. Nevertheless, it is not clear that our technology for Si devices can continue to work much longer. Here, I will discuss the driving forces, including energy dissipation, speed, area, and technological factors for the projected end‐of‐the roadmap technology. Yet, there continues to be a search for new device technologies to supplement, or replace, Si CMOS. Quantum wires have been sug‐gested in many places as a possible new technology that can provide many opportunities for enhancing chip architecture. But, the constraints on any new technology can be viewed in terms of Si cost, and the manner in which new approaches to devices can be pursued will be dis‐cussed. Some possible technologies are FinFETs, vertical quantum wires, carbon nanotubes, III‐Vs, and similar ap‐proaches. Device downsizing is only one of three driving forces that lead to Moore's Law, with increasing chip size and circuit cleverness playing an equal part. This suggests that many novel devices should not be viewed as competition to CMOS, but in the light of how they may modify the circuit architecture. Indeed, circuit clev‐erness has been as important in managing breakthroughs in the past as new processing technology. Some new op‐portunities, that arise from the nature of nanowire fabri‐cation, in these novel devices may lead to breakthroughs in the area of circuit cleverness. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)