Narrow Bus Research Articles

A novel PFM/PWM hybrid modulated single‐stage FSBB‐LLC AC‐DC converter

SummaryBy integrating the four switch buck–boost (FSBB) PFC and full‐bridge LLC resonant converter, a novel single‐stage FSBB‐LLC AC‐DC converter is proposed. Meanwhile, the corresponding PFM/PWM hybrid modulation is put forward. The proposed solution employs a dual‐loop feedback control strategy based on PFM/PWM hybrid modulation to obtain the desired bus voltage and stable output voltage. The bus voltage feedback loop is mainly used to smoothly determine the boost or buck–boost mode of FSBB PFC cell for regulating the bus voltage; the output voltage feedback loop is in charge of stabilizing the output voltage by adjusting the switching frequency or phase shifting angle. Furthermore, an optimal parameter design based on power balance principle is also derived. The experimental results of an 85 ~ 300 V input, 12V/25A output prototype demonstrate that (1) low and narrow bus voltage of 240 ~ 340 V is achieved under the entire input and output condition; (2) the LLC cell operates at DCX mode over the whole load range as the input voltage exceeds 120 V; (3) the output voltage is well regulated even under the no‐load condition; (4) ZVS feature for the shared switches is still maintained; and (5) a peak efficiency of 90.9% and PF values above 0.987 are achieved.

Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System

Many modern workloads, such as neural networks, databases, and graph processing, are fundamentally memory-bound. For such workloads, the data movement between main memory and CPU cores imposes a significant overhead in terms of both latency and energy. A major reason is that this communication happens through a narrow bus with high latency and limited bandwidth, and the low data reuse in memory-bound workloads is insufficient to amortize the cost of main memory access. Fundamentally addressing this data movement bottleneck requires a paradigm where the memory system assumes an active role in computing by integrating processing capabilities. This paradigm is known as processing-in-memory (PIM). Recent research explores different forms of PIM architectures, motivated by the emergence of new 3D-stacked memory technologies that integrate memory with a logic layer where processing elements can be easily placed. Past works evaluate these architectures in simulation or, at best, with simplified hardware prototypes. In contrast, the UPMEM company has designed and manufactured the first publicly-available real-world PIM architecture. The UPMEM PIM architecture combines traditional DRAM memory arrays with general-purpose in-order cores, called DRAM Processing Units (DPUs), integrated in the same chip. This paper provides the first comprehensive analysis of the first publicly-available real-world PIM architecture. We make two key contributions. First, we conduct an experimental characterization of the UPMEM-based PIM system using microbenchmarks to assess various architecture limits such as compute throughput and memory bandwidth, yielding new insights. Second, we present PrIM (Processing-In-Memory benchmarks), a benchmark suite of 16 workloads from different application domains (e.g., dense/sparse linear algebra, databases, data analytics, graph processing, neural networks, bioinformatics, image processing), which we identify as memory-bound. We evaluate the performance and scaling characteristics of PrIM benchmarks on the UPMEM PIM architecture, and compare their performance and energy consumption to their modern CPU and GPU counterparts. Our extensive evaluation conducted on two real UPMEM-based PIM systems with 640 and 2,556 DPUs provides new insights about suitability of different workloads to the PIM system, programming recommendations for software designers, and suggestions and hints for hardware and architecture designers of future PIM systems.

Energy Efficiency Analysis of Comb Source Carrier-Injection Ring-Based Silicon Photonic Link

Current electronic interconnections in high performance computing (HPC) systems are reaching their limit in supporting high data traffic demands. Dense wavelength-division multiplexed (DWDM) links have gained interest as they can potentially alleviate these interconnect bandwidth demands while also lowering the cost and energy consumption compared to traditional electronic links. In this article we present an analysis of a ring-based DWDM silicon photonic (SiP) link architecture with a comb laser source and p-i-n photodetectors. Specifically, we consider microring resonators (MRRs) with narrow bus waveguides and carrier-injection ring modulators. We propose a new method to select the optimal comb source setting to minimize the laser power consumption at a particular data rate. Additionally, we leverage power penalty models supported by measurements to estimate the effective received optical power at the receiver input of each of the DWDM channels which yields a bit error rate (BER) of $\text{10}^{-{\text{12}}}$ or lower. We show that the analyzed comb source has the lowest power consumption per channel for 24 consecutive lines. For these comb settings, the maximum channel data rate of non-return to zero on-off keying (NRZ-OOK) signals is 22 Gbps, and the minimum energy consumption is 3.28 $\frac{\text{pJ}}{\text{bit}}$ .

Sharing is (s)caring? Interactions between buses and bicyclists on bus lanes shared with bicyclists

This paper presents the results of an observation study of interactions between bicyclists and buses on shared bus lanes. The aim of the paper is to analyse bicyclists’ safety on bus lanes shared with bicyclists. Straight sections of two bus lanes shared with bicyclists in Belgium are observed. All interactions between bicyclists and buses over two full weeks are recorded and analysed. Additionally, the lateral position and riding speed of bicyclists that are in interaction with buses are compared with the behaviour of bicyclists that are not in interaction with buses. One of the observed bus lanes is in line with road design guidelines in a number of countries that state that a sufficiently narrow bus lane (<3.5m) is hypothesised to be safer than a somewhat wider bus lane; the other observed bus lane is deemed too wide according to these guidelines and is hypothesised to lead to close overtaking manoeuvres.The results show that close interactions between bicyclists and buses are relatively frequent on both types of analysed bus lanes. Close overtaking manoeuvres (a bus overtakes a bicyclist with a lateral distance less than 1m) as well as close bicycle-following situations (a bus drives behind a bicyclist with a time gap less than 2s) are quite common on both analysed bus lanes. The analyses could not confirm the hypothesis that a sufficiently narrow bus lane is safer than a wider bus lane. On the contrary, close interactions seem even slightly more common on the narrower bus lane. Slightly more close overtaking manoeuvres take place on the narrower bus lane, but the difference is not statistically significant. Additionally, more bicycle-following situations take place on the narrower bus lane because overtaking is more difficult. The results show that buses often maintain a close time gap in these situations. The overtaking speed of the buses is, however, significantly higher on the wider bus lane compared to the narrower one.Moreover, the presence of a bus has an influence on the behaviour of bicyclists. Bicyclists who get overtaken by a bus ride more closely to the edge of the road than bicyclists who are not in interaction with a bus. While the road design guidelines assume that bicyclists take up a width of one meter from the edge on bus lanes shared with bicyclists, the observations show that bicyclists take up much less space while being overtaken. The presence of a bus does not have a significant influence on the standard deviation of the lateral position of the bicyclist. On the narrower bus lane, some findings suggest that bicyclists who are involved in an interaction with a bus ride faster than bicyclists who are not involved in an interaction with a bus.

Roll-type photolithography for continuous fabrication of narrow bus wires

This paper presents a continuous patterning method to enhance the productivity of metallic microstructure fabrication. The minimum exposure time and the optimum ultraviolet (UV) intensity were determined for the photoresist (PR) to develop micro PR patterns in continuous roll-type photolithography. To confirm the efficiency of continuous roll-type photolithography, wet etching was performed instead of dry etching as a post-lithography process. Parametric study results showed that the minimum exposure time required for sufficient PR reaction during continuous roll-type photolithography was 0.2 s under 1000 mW cm−2 of UV intensity. This study demonstrated roll-type photolithography and determined the highest production speed for continuous roll-type photolithography to be 24 mm s−1. Continuous photolithography and wet etching were employed to produce narrow copper bus wires for a bezel-less display panel, indicating the practical applications of continuous roll-type photolithography.

Vacuum-Free Continuous Fabrication for Forming Narrow Bus Wires

Photolithography is undoubtedly the most widely used patterning method for the fabrication of micro-and nanofeatures, despite the recent development in some unconventional fabrication techniques that are poised to take over certain applications. But photolithography is still the main fabrication method in industry. To step forward in many applied areas, however, large-area, continuous fabrication system needs to be developed. However photolithography has not been extended to large area continuous patterning like other printing technologies. Photolithography is currently based on wafer scale fabrication and metal deposition process is performed under high vacuum condition. Here we report the development of continuous roll type contact photolithography which is termed photo roll lithography (PRL) and vacuum-free metal filling method. Continuous patterning is achieved was by employing a flexible photomask with Al patterns, which was fabricated by conventional photolithography method. Also, metal nanopowder was stuffed in fabricated PR patterns by puffs, instead of conventional deposition methods. As a feasible application, we demonstrated a fabrication of narrow bus wire for using on display devices.

Buffer-on-board memory systems

The design and implementation of the commodity memory architecture has resulted in significant performance and capacity limitations. To circumvent these limitations, designers and vendors have begun to place intermediate logic between the CPU and DRAM. This additional logic has two functions: to control the DRAM and to communicate with the CPU over a fast and narrow bus. The benefit provided by this logic is a reduction in pin-out to the memory system and increased signal integrity to the DRAM, allowing faster clock rates while maintaining capacity. While the few vendors utilizing this design have used the same general approach, their implementations vary greatly in their nontrivial details. A hardware-verified simulation suite is developed to accurately model and evaluate the behavior of this buffer-onboard memory system. A study of this design space is used to determine optimal use of the resources involved. This includes DRAM and bus organization, queue storage, and mapping schemes. Various constraints based on implementation costs are placed on simulated configurations to confirm that these optimizations apply to viable systems. Finally, full system simulations are performed to better understand how this memory system interacts with an operating system executing an application with the goal of uncovering behaviors not present in simple limit case simulations. When applying insights gleaned from these simulations, optimal performance can be achieved while still considering outside constraints (i.e., pin-out, power, and fabrication costs).

Narrow bus encoding for low-power DSP systems

High levels of integration in integrated circuits often lead to the problem of running out of pins. Narrow data buses can be used to alleviate this problem provided that the degraded performance due to wait cycles can be tolerated. We address bus coding methods for low-power core-based systems incorporating narrow buses. We show that transition signaling combined with bus-invert coding, which we call BITS coding, is particularly suitable for the data patterns of typical DSP applications on narrow data buses. The application of BITS coding to real circuit design is limited by the extra bus line introduced, which changes the pinout of the chip. We propose a new coding method, which does not require the extra bus line but retains the advantage of BITS.