Nanoscale Metal Oxide Semiconductor Field Effect Transistor Research Articles

Analysis of Channel Current Noise in Small Nanoscale Metal Oxide Semiconductor Field Effect Transistors.

The shrinkage of metal oxide semiconductor field effect transistor (MOSFET) to the small size of the nanoscale results in changes in their channel current noise composition. This paper determines the channel current noise composition of 90nm MOSFET through experiments, and according to the device material and noise characteristics analysis, the channel current noise of 90nm and below is obtained, which not only contains thermal noise and suppressed channel shot noise, but also adds suppressed gate tunneling shot noise and cross-correlation noise. Then, Monte Carlo simulation of 10nm MOSFET noise is further used to determine the channel current composition of small size nanoscale devices. Subsequently, based on the device structure and fundamental characteristics of channel current noise, the channel current noise model is established. Finally, this model is employed to analyze the relationship between thermal noise, suppressed shot noise, cross-correlation noise, and channel current noise in relation to bias parameters and device characteristics. The theoretical results are basically consistent with the experimental and the simulated results, and the channel noise increases with the increase of bias voltage. This achievement holds promise for enhancing the operational efficiency, reliability, and lifetime of nanoscale small-sized MOSFET devices.

Modeling of non-intrinsic noise in nanometer metal oxide semiconductor field effect transistors

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices.

Analysis of thermal noise characteristics in 10 nm metal oxide semiconductor field effect transistor

<sec>Small size metal-oxide-semiconductor field effect transistor (MOSFET), owing to their high theoretical efficiency and low production cost, have received much attention and are at the frontier of transistors. At present, their development is bottlenecked by physical limits due to equal scaling down of devices, which requires further improvement in terms of materials choice and device fabrication. As the MOSFET devices scale down to nanometer scale, on the one hand, the resulting short channel effect affects severely the thermal noise property; on the other hand, it makes the ratio of thermal noise in the gate, source, drain and substrate regions become higher and higher. However, the traditional thermal noise model mainly considers thermal noise of large-size devices, and its model does not consider the channel saturation region. In view of this, it is necessary to establish a small size MOSFET thermal noise model and analyze its characteristics.</sec><sec>At present, there are some researches on MOSFET thermal noise, but they mainly focus on the thermal noise in channel region of large size nanoscale MOSFET. In the present work, according to the device structure and inherent thermal noise characteristics, we establish a thermal noise model for MOSFETs of 10 nm feature size. The model includes contributions of substrate region, gate-source-drain region, and channel region. In the channel region is also included the thermal noise related to the device saturation regime. Using such a model, the dependence of channel thermal noise and total thermal noise on the device bias condition and device parameters are investigated, evidencing the existence of thermal noise in the device saturation regime, which are consistent with the experimental results in the literature. The thermal noise increases with the gate voltage and source-drain voltage rising as the device structure shrinks. In a temperature range of 100–400 K, the thermal noise is basically on the order of 10<sup>21</sup>, indicating that the temperature has a great influence on the thermal noise. The thermal noise model established in this work can be applied to analyzing the noise performances of small size MOSFET devices, and the conclusions drawn from the present study are beneficial to improving the efficiency, lifetime, and response speed of MOSFETs on a nanometer scale.</sec>

The analysis of channel noise properties and its correlation in nanoscale metal–oxide–semiconductor field-effect transistors

During the traditional channel noise modeling of nanoscale MOSFETs, neither the suppression of shot noise by Fermi and Coulomb effects nor the cross correlation noise between the source current noise and gate current noise is considered. However, they should not be ignored. In this study, the channel noise of a 22 nm MOSFET is tested experimentally, and the results show that the suppressed shot noise, the thermal noise, and the cross correlation noise are the main types of channel noises in nano-MOSFETs. Furthermore, according to the physical structure and characteristics of the MOSFET, a noise model, including the elements of shot noise, thermal noise, and cross correlation noise, is derived, which considers the influence of the shot noise suppressed by either the Fermi or Coulomb effects. Based on the model, the variation of noise with the channel length, temperature, source–drain voltage, and gate voltage is analyzed. The results are consistent with the experiments and theories in the literature.

Nanoscale MOSFET as a Potential Room-Temperature Quantum Current Source.

Nanoscale metal-oxide-semiconductor field-effect-transistors (MOSFETs) with only one defect at the interface can potentially become a single electron turnstile linking frequency and electronic charge to realize the elusive quantized current source. Charge pumping is often described as a process that ‘pumps’ one charge per driving period per defect. The precision needed to utilize this charge pumping mechanism as a quantized current source requires a rigorous demonstration of the basic charge pumping mechanism. Here we present experimental results on a single-defect MOSFET that shows that the one charge pumped per cycle mechanism is valid. This validity is also discussed through a variety of physical arguments that enrich the current understanding of charge pumping. The known sources of errors as well as potential sources of error are also discussed. The precision of such a process is sufficient to encourage further exploration of charge pumping based on quantum current sources.

Polarization Effect Due to Discreteness of Dopants in Nanoscale MOSFETs

We study the polarization effects associated with the discreteness of dopants at the interface in metal–oxide–semiconductor field-effect-transistors (MOSFETs) by drift-diffusion simulations. A charge distribution model, which reproduces the long-range Coulomb potential consistently with a dielectric mismatch at the interface between semiconductor substrate and oxide, is incorporated into simulations, and the impact on statistical variability in threshold voltage in nanoscale MOSFETs is clarified. We explicitly and quantitatively show, for the first time, that the threshold voltage is shifted due to the polarization charge at the interface induced by the discreteness of dopants in the semiconductor substrate.

Influence of Quantum Capacitance on Charge Carrier Density Estimation in a Nanoscale Field-Effect Transistor with a Channel Based on a Monolayer WSe2 Two-Dimensional Crystal Semiconductor

A critical analysis of charge carrier statistics influenced by quantum capacitance is carried out in order to predict the electrical performance of a nanoscale metal–oxide–semiconductor field-effect transistor (MOSFET) with a channel made of a monolayer tungsten diselenide (WSe2) two-dimensional (2D) crystal semiconductor. Since quantum capacitance originating from two-dimensional electron gas in a quantum well or an inversion layer does not completely screen the quasistatic electric field during applied gate voltage, the partial penetration of an external electric field through the 2D semiconductor channel will generate excess charge carriers; thus quantum capacitance will play an important role in determining the overall charge carrier density in the channel. Therefore, common methods used to extract charge carrier density in the channel for three-dimensional (3D) crystal semiconductors will yield inaccurate results when used for 2D crystal semiconductors. To address this issue, this study proposes a modified approach for extracting charge carrier density in WSe2-based 2D semiconductors by combining the appropriate carrier statistics with consideration of quantum capacitance. In addition, the study investigates the effect of interface traps on overall capacitance, which may influence the electrical performance of a nanoscale MOSFET with monolayer WSe2 as a channel material.

Comparitive study of electrical properties of carbon nano tube (CNT) and silicon nanowire (SNW) MOSFET devices

Metal oxide semiconductor field effect transistor (MOSFET) is a semiconductor device used in many electronic devices for amplification and switching electrical signals. MOSFET downscaling has been the driving force towards the technological advancement, but continuous scaling down of MOSFET causes problem of high power dissipation, high leakage current, Short Channel Effects (SCEs), excessive process variation and reliability issues. In this work, comparative study of electrical properties of carbon nanotube (CNT) and silicon nanowire (SWN) were carried out using CNT and SNW as channel materials, silicon dioxide as the gate dielectric, silicon substrate as base material. The analysis is carried out using FETTOY simulating software for oxide thickness (0.3,0.5,0.7,0.9 and 1.2nm). The results show that carbon nanotube channel material have highest transconductance (g m ) of 1.00 x 10 -4 S , highest conductance ( g 4 ) of 4.00 x 10 -6 S, highest carrier injection velocity ( v in j )of 5.43 x 10 5 m/s, highest on current (Ion) of 59.79uA, at oxide thickness of 0.3nm when used as MOSFET device and improved short channel effects with subthreshold swing (S) of 67.79 mV/dec and drain induced barrier lowering (DIBL) of 39.67. More results such as drain current ( I d ) versus gate voltage ( V g ) , quantum capacitance (QC) versus gate voltage (V g ) , and average velocity of mobile electron versus gate voltage ( V g ) for all devices are also investigated. Various results obtained indicate that CNT has the higher performance of decreasing gate capacitance with decrease in oxide thickness ( T Ox ) in deep nanometer regime. This decrease in gate capacitance is observed at a gate voltage of 0.5V and above which leads to the reduction of propagation delay, lower leakage current, low power dissipation, short channel effects (SCEs) as compared to silicon nanowire MOSFET device. KEYWORDS : Ballistic nanoscale MOSFET, Channel materials, FETTOY simulating software, Short channel effects (SCEs), Drain Induces Barrier Lowering (DIBL)

PHYSICS OF NANOTRANSISTORS: STRUCTURE, METRICS, AND CONTROL

The transistor is the key element of almost any electronic device. By the end of the 20th century, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) sizes had reached a nanoscale, and the nanotransistor itself was the first of all nanoscale electronic devices to be the object of large-scale industrial production. Today, the length of the conduction channel of the transistor has approached 10 nm, which is several orders of magnitude lower than in the first MOSFET.The task of this new series of our tutorial reviews directed to serve researchers, university teachers and students, is to discuss the physical models and principles underlying the functioning of nanoscale MOSFETs and based both on the traditional «top – down» approach and on a more modern approach originating in the works of Rolf Landauer, developed later by Suprio Datta and Mark Lundstrom.

Analytical gate fringe capacitance model for nanoscale MOSFET with layout dependent effect and process variations

In this paper, we present an analytical closed model for the gate to source/drain fringing capacitance (Cf) of nanoscale metal oxide semiconductor field effect transistors (MOSFETs), with the consideration of layout dependent effects and process fluctuations. A kind of field-poly structure on shallow trench isolation (STI) is used to separate Cf from other gate-around parasitic capacitances. A significant layout-dependent-effect is found in Cf for the case with high contact density. Based on the device structure, Cf is divided and analytically modeled by three dual-k perpendicular-plate capacitances. The effects of gate to contact space (CPS), contact to contact space (CCS) and the process variations, such as the over-etching of source/drain contact, are taken into account. The proposed model is validated on 40 nm MOSFETs, with a series of layout parameters, and good agreement is obtained between the modeled and measured data over a large range of CPS and CCS. The proposed model can improve the precision for digital and RF circuit simulation in sub-nanometer technology generation.

Superior electrical characteristics of novel nanoscale MOSFET with embedded tunnel diode

Metal Oxide Semiconductor Field Effect Transistors (MOSFET) play an important role in electronic industry development. To improve the electrical characteristics of these transistors in this paper, a new structure is proposed to reduce floating body effect, lattice temperature, and short channel effects. The main mechanism for controlling these critical issues is using an embedded tunnel diode. The tunnel diode formed by heavily doped N and P silicon windows which are embedded into the buried oxide layer. The accumulated holes are effectively released by the tunnel current of the tunnel diode. The simulation with ATLAS simulator shows that the proposed structure works properly and the important parameters such as subthreshold slope, off current, voltage gain, and maximum lattice temperature improve in comparison with the conventional nanoscale MOSFET.

Gate Tunnelling Current Model for Nanoscale MOSFETs with Varying Surface Potential

ABSTRACTAt nanoscale, the channel of metal oxide semiconductor field effect transistors (MOSFETs) acts like a potential well within which electron energy levels are quantized and a nonzero wavefunction is obtained at the oxide–semiconductor interface. As a result the gate tunnelling current has emerged a significant constraint in respect of scaling of ultrathin gate oxides. We have developed an analytical model considering varying surface potential with applied voltage for evaluating gate tunnelling current through thin dielectrics in nanoscale MOSFETs. The electron wavefunction has been calculated by treating the band profile in the channel as a triangular potential well. The tunnelling probability through the gate oxide has been evaluated using Jeffreys–Wentzel–Kramers–Brillouin approximation method. The tunnelling current density is estimated from the evaluated interface wavefunction along with the tunnelling probability. The results from the present model compare well with the published Mondal–Dutta model and the experimental data. The novelty of the present model lies in its simplicity and its analyticity requiring much less computational efforts for its implementation.

Effect of film properties for non-linear DPL model in a nanoscale MOSFET with high-k material: ZrO2/HfO2/La2O3

Numerical simulation of non-linear non-Fourier heat conduction within a nano-scale metal–oxide–semiconductor field-effect transistor (MOSFET) is presented under the framework of Dual-Phase-Lag model including the boundary phonon scattering. The MOSFET is modeled in four cases of: (I) thin silicon slab, (II) including uniform heat generation, (III) double-layered buried oxide MOSFET with uniform heat generation in silicon-dioxide layer, and (IV) high-k/metal gate transistor. First, four cases are studied under four conditions of (a) constant bulk and (b) constant film thermal properties, (c) temperature-dependent properties of bulk silicon, and (d) temperature-dependent thermal properties of film silicon. The heat source and boundary conditions are similar to what existed in a real MOSFET. It is concluded that in all cases, considering the film properties lowers the temperature jump due to the reduction of the Knudsen number. Furthermore, the speed of heat flux penetration for film properties is less than that of the cases concerning bulk properties. Also, considering the temperature-dependent properties drastically changes the temperature and heat flux distributions within the transistor, which increases the diffusion speed and more, decreases the steady state time. Calculations for case (III) presents that all previous studies have underestimated the value of the peak temperature rise by considering the constant bulk properties of silicon. Also, it is found that among the high-k dielectrics investigated in case (IV), zirconium dioxide shows the least peak temperature rise. This presents that zirconium dioxide is a good candidate as far as the thermal issues are concerned.

A Statistical Model for the Headed and Tail Distributions of Random Telegraph Signal Magnitudes in Nanoscale MOSFETs

Trapping-detrapping of a single electron via an individual trap in metal-oxide–semiconductor field-effect transistor (MOSFET) gate dielectric constitutes two-level random telegraph signals. Recent 3-D technology computer-aided design (TCAD) simulations, on an individual MOSFET, revealed that with the position of the trap as a random variable, resulting random telegraph signals relative magnitude <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(\Delta I_{{\boldsymbol {{d}}}}/I_{{\boldsymbol {{d}}}}\) </tex-math></inline-formula> in the subthreshold current at low drain voltage can have two distinct distributions: a headed one for a percolation-free channel and a tail one for a percolative channel. The latter may be effectively treated by a literature formula: ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(\Delta I_{{\boldsymbol {{d}}}}/I_{{\boldsymbol {{d}}}})=(I_{\mathbf {loc}}/I_{{\boldsymbol {{d}}}})^{\mathrm {\mathbf {2}}}\) </tex-math></inline-formula> , where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(I_{\mathbf {loc}}\) </tex-math></inline-formula> is the local current around the trap. In this paper, we show how to make this formula practically useful. First, we conduct 3-D TCAD simulations on a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(35\times 35\) </tex-math></inline-formula> -nm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(^{\mathrm {\mathbf {2}}}\) </tex-math></inline-formula> channel to provide <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(\Delta I_{{\boldsymbol {{d}}}}/I_{{\boldsymbol {{d}}}}\) </tex-math></inline-formula> for a few positions of the trap. This leads to a new statistical model in closed form, which can reproduce headed distributions. Straightforwardly, key criteria are drawn from the model, which can act as guidelines for the adequate use of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">\(I_{\mathbf {loc}}/I_{{\boldsymbol {{d}}}}\) </tex-math></inline-formula> formula. Extension to threshold voltage shift counterparts, from subthreshold through transition to inversion, is successfully achieved. Importantly, use of the model may overcome the drawbacks of the statistical experiment or simulation in the field.

Performance Benchmarking of 32 nm Predictive Technology Model CMOS with Silicon Nanowire Physic-Based Compact Model of Field-Effect Transistors for Digital Logic Applications

New variation of nanostructures are introduced and developed to sustain Moore's Law as device dimension is scaled drastically. Among those low dimensional technological innovation is silicon (Si) nanowire field-effect transistor (NWFET). The usefulness of Si NWFET is its compatibility with existing complementary metal-oxide semiconductor (CMOS) technology that been widely pursued for more than four decades. Device simulation of nanowire is essential to explore physics in depth and to assess, quantify and benchmark the device performance metrics with a nanoscale metal-oxide semiconductor field-effect transistor (MOSFET). SPICE model of Si NWFET is constructed based on the device model proposed by researchers from Purdue University. A semi-empirical solution of the self-consistent is presented so that the device model is made portable and can be simulated in SPICE and other platform. Then, silicon-based digital logic circuit namely inverter, NOR and NAND are simulated and analysed. The circuit performances of nanowire digital gates are then compared against 32 nm MOSFET in terms of energy-delay product, power-delay product, propagation delay and average power dissipation. The results shown that silicon nanowires perform better than 32 nm MOSFET generally due to the high velocity transport of quasi ballistic carriers and superior gate control.

Monte Carlo analysis of dynamic characteristics and high-frequency noise performances of nanoscale double-gate MOSFETs

In this paper, a full-band Monte Carlo simulator is employed to study the dynamic characteristics and high-frequency noise performances of a double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross-correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NFmin), and so on are employed to evaluate the noise performances. To show the outstanding radio-frequency performances of the DG MOSFET, a single-gate silicon-on-insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high-frequency noise performances, owing to its inherent short-channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.

A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect

In this paper, we propose a unique feature exhibited by novel nanoscale metal oxide semiconductor field effect transistors (MOSFETs) with an undoped buried region (UBR) under the channel and a buried oxide only under the source and drain region. The key idea in this work is suppression of the self-heating effect and gate–substrate capacitance improvement by modifying the buried layer. As a result, we demonstrate that the proposed structure called undoped buried region MOSFET (UBR-MOSFET) exhibits gate–substrate improvement in addition to excellent temperature performance when compared to conventional structures. Using two-dimensional and two-carrier device simulation, we have examined various design issues of the UBR-MOSFET and provided the reasons for the improved performance. The simulated results show that the novel structure is a suitable device for high temperature and electrical performances.

The Generation Process of Interface Traps by Hot-Carrier Injection in Nanoscale Metal–Oxide–Semiconductor Field-Effect Transistors

The generation process of interface traps by hot-carrier injection in nanoscale metal–oxide–semiconductor field-effect transistors (MOSFETs) was evaluated by the charge pumping (CP) method, and degradation of the threshold voltage by these interface traps was studied. The generation process is found to follow the conventional ΔIcp∼tn relationship for a short period of stress and then shows a saturation behavior after longer stress times. The factors that determine the interface trap generation before and after saturation are analyzed. A new equation to describe the generation process is given.

The Generation Process of Interface Traps by Hot-Carrier Injection in Nanoscale Metal–Oxide–Semiconductor Field-Effect Transistors

The Generation Process of Interface Traps by Hot-Carrier Injection in Nanoscale Metal–Oxide–Semiconductor Field-Effect Transistors

An Approach Based on Sensitivity Analysis for the Evaluation of Process Variability in Nanoscale MOSFETs

We propose an approach to evaluate the effect on the threshold-voltage dispersion of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs) of line-edge roughness, surface roughness, and random dopant distribution. The methodology is fully based on parameter sensitivity analysis, performed by means of a limited number of technology computer-aided design simulations or analytical modeling. We apply it to different nanoscale transistor structures, i.e., bulk 45-nm n-channel, 32-nm ultrathin-body silicon-on-insulator, and 22-nm double-gate MOSFETs. In all cases, our approach is capable of reproducing with very good accuracy the results obtained through 3-D atomistic statistical simulations at a small computational cost. We believe that the proposed approach can be a powerful tool to understand the role of the main variability sources and to explore the device design parameter space.