Nanocrystalline Silicon Thin-film Transistors Research Articles

Modeling triplet spike timing dependent plasticity using a hybrid TFT-memristor neuromorphic synapse

Triplet-based Spike Timing Dependent Plasticity (TSTDP) is an enhanced synaptic plasticity rule which can be implemented using new nano-scale technologies. Nanocrystalline-silicon thin film transistors (TFT) and memristors are of these nano-scale devices which can be integrated into three-dimensions using low-temperature processing. This paper proposes a new hybrid TFT-memristive circuit that implements the TSTDP. The proposed circuit is composed of two nanoparticle memory-TFTs in series with a current/charge controlled memristor, as the synapse. Our simulation results, using spike pairs with various timing intervals and frequencies, as well as different spike triplets, demonstrate a particularly close match to realistic biological measurements.

Dual-mechanism modelling of instability in nanocrystalline silicon thin film transistors under prolonged gate-bias stress

A dual-mechanism model of the threshold voltage (VT) shift is proposed for the plasma deposited hydrogenated nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs) stressed under relatively high gate-bias for ∼ 106 s. ΔVT versus stress time experimental behavior is modelled by accurate fitting of the combination of stretched exponential and logarithmic dependences. Without such superposition as it is commonly done in other works, i.e. by using any single dependence only, no successful fit was obtained for the VT shift data at hand. While the stretched exponential behavior is found to be dominant at short stress times, the logarithmic behavior dominates at long stress times. These mathematically distinct behaviors are demonstrated to be attributed to totally distinct TFT instability mechanisms: defect state creation within the nc-Si:H channel layer and charge trapping in the gate insulator. The relaxation data of the stressed TFTs under room temperature support the simultaneous presence of these mechanisms during stressing. In addition, different nanocrystalline volume fractions of the nc-Si:H channel layers of two TFT sets resulted in different ΔVT versus stress time data, which also supports the dual-mechanism instability model.

Model for threshold voltage instability in top-gated nanocrystalline silicon thin film transistor

The analytical model for the threshold voltage instability in top-gated staggered nanocrystalline silicon thin-film transistor is reported. This novel model includes the effect of various physical parameters like grain size, gate insulator thickness, doping density and grain boundary trapping state on the threshold voltage shift which is never reported earlier. It is observed that the higher trap density, greater doping concentration and larger gate insulator thickness provide lesser threshold voltage shift. Further, it is found from the results of grain size analysis that if grain size is smaller than threshold voltage shift decreases with decrease in grain size. However, if grain size is larger $$(\hbox {D}_\mathrm{g} > 20\,\hbox {nm})$$(Dg>20nm) then device become stable and shows negligible threshold voltage shift. In this paper, threshold voltage shift under gate bias voltage is also analyzed and result reveals that threshold voltage increases with the bias voltage. The calculated results are compared with experimental data. The close match between the two confirms the validity of proposed study.

Nonvolatile Memory Device Using Mobile Protons via Insertion Hydrogen Neutral Beam Treatment Process between SiO2 Deposition Processes at Room Temperature

We demonstrated the nonvolatile memory functionality of nano-crystalline silicon (nc-Si) thin film transistors (TFTs) using mobile protons that are generated by very short time hydrogen neutral beam (H-NB) treatment at room temperature (25 °C). The whole memory fabrication process kept under 50 °C (except SiO2 deposition process; 300 °C). These nc-Si devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. Our study will further provide a useful route of creating memory functionality and incorporating proton-based storage elements onto a probability of next generation flexible memorable electronics such as low power consumption flexible display panel.

Theoretical determination of the impact of channel morphology and quantum size effects on the surface potential of nanocrystalline silicon thin film transistors

In this work, we propose an analytical model allowing the calculation of nanocrystalline silicon thin film transistors surface potential by considering a granular morphology of silicon nanocrystallites forming the channel. Results show that, according to the quantum effects on dielectric constant and band gap, the surface potential values are strongly related to the silicon crystallites structure in terms of size and geometry. The comparison of our results with existing research data shows a good agreement between the surface potential shapes and an interesting difference in the surface potential variations related to the morphology specificity considered in our theoretical approach.

(Invited) Nanocrystalline Silicon Thin Film Transistors for Neuromorphic Applications

This paper briefly reviews some of our recent work on the fabrication, modeling and characterization of neuromorphic circuits using nanocrystalline-silicon (nc-Si) thin-film transistors (TFTs) and memristive (resistive switch) devices (1-11). SPICE models of our fabricated devices are presented. Complex synaptic and learning behavior is demonstrated as a natural outcome of using these specific devices. The fabrication processes are consistent with the use of glass or flexible substrates. Therefore, the neuromorphic architecture may provide for information processing that is more efficient than that expected for conventional TFT circuitry.

Quantum size impacts on the threshold voltage in nanocrystalline silicon thin film transistors

Based on the analysis of Poisson equation, an analytical threshold voltage model including quantum size effect of nc-TFTs (nanocrystalline silicon thin film transistor) has been proposed in this paper. The results demonstrate that the proposed simplified expression of threshold voltage agree perfectly with numerical calculation. The threshold voltage in nc-TFTs strongly depends on the size of silicon grain when the size of silicon grain is less than 20nm. Such a strong dependent relation results from the large changes in the bandgap and dielectric constant due to quantum size effects when the size of silicon grain is in the regime of nano-scale. The theoretical investigation also demonstrates that the grain boundary trap density compared to the active dopant density gives a main contribution to the threshold voltage. This implies that the grain size must be larger than 30nm in order to avoid threshold voltage variation from different technological processes.

Spike-Timing-Dependent Plasticity Using Biologically Realistic Action Potentials and Low-Temperature Materials

Spike-timing-dependent plasticity (STDP) is a fundamental learning rule observed in biological synapses that is desirable to replicate in neuromorphic electronic systems. Nanocrystalline-silicon thin film transistors (TFTs) and memristors can be fabricated at low temperatures, and are suitable for use in such systems because of their potential for high density, 3-D integration. In this paper, a compact and robust learning circuit that implements STDP using biologically realistic nonmodulated rectangular voltage pulses is demonstrated. This is accomplished through the use of a novel nanoparticle memory-TFT with short retention time at the output of the neuron circuit that drives memristive synapses. Similarities to biological measurements are examined with single and repeating spike pairs or different timing intervals and frequencies, as well as with spike triplets.

Logic Gates and Ring Oscillators Based on Ambipolar Nanocrystalline-Silicon TFTs

Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) are well suited for circuit applications that require moderate device performance and low-temperature CMOS-compatible processing below 250°C. Basic logic gate circuits fabricated using ambipolar nc-Si TFTs alone are presented and shown to operate with correct outputs at frequencies of up to 100 kHz. Ring oscillators consisting of nc-Si TFT-based inverters are also shown to operate at above 20 kHz with a supply voltage of 5 V, corresponding to a propagation delay of <10 μs/stage. These are the fastest circuits formed out of nanocrystalline silicon TFTs to date. The effect of bias stress degradation of TFTs on oscillation frequency is also explored, and relatively stable operation is shown with supply voltages >5 V for several hours.

Submicron Ambipolar Nanocrystalline Silicon Thin-Film Transistors and Inverters

Nanocrystalline silicon (nc-Si) thin-film transistors (TFTs) fabricated at a maximum processing temperature of 250 °C operate with high field-effect mobility compared with amorphous-silicon TFTs. By reducing the oxygen content in the channel layer, ambipolar behavior can be obtained. Two levels of electron-beam lithography are employed to fabricate nc-Si TFTs with nanoscale dimensions that operate without significant short-channel effects for gate lengths down to 200 nm. The TFTs have current-voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> ) characteristics with on-off ratio >; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> at ±1 V drain voltage and low threshold voltage shift. Simulation Program with Integrated Circuit Emphasis (SPICE) software is used to model the TFTs, and it is validated by performing the fit to devices of different dimensions. An inverter constituent of nc-Si TFTs offers high voltage gain (10-12) and frequency response better than 2 MHz. The crowbar current associated with the inverter can be minimized by using an optimized geometry ratio based on the leakage currents of the TFTs. An amplifier circuit is also demonstrated, offering an ac gain in the frequency range of 100 Hz-10 kHz. SPICE simulations of the inverter and amplifier show close agreement with measured data. The fabricated devices are well suited for use in high-density architectures.

A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTs

This paper presents a novel pixel design for active matrix organic light emitting diode (AM-OLED) displays using nanocrystalline silicon thin-film transistors (TFTs). The proposed pixel design can effectively reduce the variation of its stored display data caused by the leakage current of nanocrystalline silicon TFTs, which can in turn increase the contrast resolution of AM-OLED displays. With a proper setting of its capacitors, the proposed pixel design can achieve a 5.55× reduction on its display-data variation while requiring only a 1.15× write time when compared to the typical pixel design. The aperture ratio resulting from the layout of the proposed pixel design can also be maintained above 40%, which satisfies the specification of most AM-OLED displays. A series of simulations as well as measurement results are provided to validate the effectiveness of the proposed pixel design.

Hebbian Learning in Spiking Neural Networks With Nanocrystalline Silicon TFTs and Memristive Synapses

Characteristics similar to biological neurons are demonstrated in SPICE simulations of spiking neuron circuits comprised of submicron nanocrystalline silicon (nc-Si) thin-film transistors (TFTs). Utilizing these neuron circuits and corresponding device models, the properties of a two-neuron network are explored. The synaptic connection consists of a single nc-Si TFT and a memristor whose conductance determines the synaptic weight. During correlated spiking of the pre- and postsynaptic neurons, the strength of the synaptic connection increases. Conversely, it is diminished when the spiking is uncorrelated. This synaptic plasticity and Hebbian learning are essential for performing useful computation and adaptation in large-scale artificial neural networks. The importance of the result is augmented by the fact that these properties are demonstrated using models based on measured data from devices with potential for 3-D integration into a nanoscale architecture with extremely high device density.

DC and AC Gate-Bias Stability of Nanocrystalline Silicon Thin-Film Transistors Made on Colorless Polyimide Foil Substrates

ABSTRACTStaggered bottom-gate hydrogenated nanocrystalline silicon (nc-Si:H) thin-film transistors (TFTs) were demonstrated on flexible colorless polyimide substrates. The dc and ac bias-stress stability of these TFTs were investigated with and without mechanical tensile stress applied in parallel to the current flow direction. The findings indicate that the threshold voltage shift caused by an ac gate-bias stress was smaller compared to that caused by a dc gate-bias stress. Frequency dependence of threshold voltage shift was pronounced in the negative gate-bias stress experiments. Compared to TFTs under pure electrical gate-bias stressing, the stability of the nc-Si:H TFTs degrades further when the mechanical tensile strain is applied together with an electrical gate-bias stress.

Photo-Induced Instability of Nanocrystalline Silicon TFTs

We examine the instability behavior of nanocrystalline silicon (nc-Si) thin-film transistors (TFTs) in the presence of electrical and optical stress. The change in threshold voltage and sub-threshold slope is more significant under combined bias-and-light stress when compared to bias stress alone. The threshold voltage shift <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(\Delta{V}_{T})$</tex> </formula> after 6 h of bias stress is about 7 times larger in the case with illumination than in the dark. Under bias stress alone, the primary instability mechanism is charge trapping at the semiconductor/insulator interface. In contrast, under combined bias-and-light stress, the prevailing mechanism appears to be the creation of defect states in the channel, and believed to take place in the amorphous phase, where the increase in the electron density induced by electrical bias enhances the non-radiative recombination of photo-excited electron-hole pairs. The results reported here are consistent with observations of photo-induced efficiency degradation in solar cells.

Characterization of traps in the gate dielectric of amorphous and nanocrystalline silicon thin-film transistors by 1/f noise

The low frequency noise technique is used to obtain the volume profile of traps in the SiNx gate dielectric of hydrogenated amorphous silicon (a-Si:H) and nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs). In both a-Si:H and nc-Si:H TFTs, within the range of probing depth in the gate dielectric, the traps have a uniform spatial distribution which is consistent with the observed pure 1/f noise. The experimental results show that the gate dielectric trap properties near the interface are dependent on the channel material with the trap density in nc-Si:H TFTs being much smaller in comparison with the a-Si:H TFTs.

The Influence of Electromechanical Stress on the Stability of Nanocrystalline Silicon Thin Film Transistors Made on Colorless Polyimide Foil

Staggered bottom-gate hydrogenated nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs) fabricated on flexible transparent polyimide substrates were investigated. The saturation electron field-effect mobility and electrical bias-stress stability of these TFTs were evaluated under applied tensile mechanical strain parallel to the source-drain direction. The mobilities increased accompanying with deteriorated electrical stabilities as the applied tensile strain increased. The power-law dependence between threshold voltage shift and gate-bias stressing time indicates that the instability is mainly caused by the state creation at the interface between nc-Si:H channel and gate dielectric.

(Invited) Nanocrystalline Silicon Thin Film Transistors

We review performance characteristics of top- and bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs). Top gate TFTs with nc-Si active layer of nearly 80% crystallinity along with a silicon oxide gate dielectric produce high electron mobilities; values two orders higher than the amorphous silicon counterpart. In contrast, bottom-gate TFTs with silicon nitride gate dielectric and nc-Si active layer of similar crystallinity yield a mobility that is only marginally better than amorphous silicon TFT. However, they are highly stable with no visible presence of defect state creation in the active layer. In contrast, top-gate TFTs suffer from severe charge trapping in the low quality oxide gate dielectric.

Nanocrystalline silicon fabrication by conventional plasma enhanced chemical vapor deposition for bottom gate thin film transistor

Nanocrystalline silicon was successfully fabricated using conventional plasma enhanced chemical vapor deposition (PECVD) for bottom gate thin film transistor. This was accomplished by promoting nucleation rate in the initial stage of silicon growth by H 2 or SF 6 plasma treatment of the surface of silicon nitride (SiN x) films. Microstructure of hydrogenated nanocrystalline silicon (nc-Si:H) films confirmed the crystallization of silicon, and nanocrystalline silicon thin film transistor exhibited excellent stability.

The effect of post-hydrogen annealing and multilayer channel structure on nano-crystalline silicon thin film transistor performance

The effect of multilayer channel structure and post-hydrogen annealing (PHA) on the performances of nano-Si thin film transistors (nc-Si TFTs) prepared by a hot wire chemical vapour deposition system on Si substrates was investigated. The experimental results showed that the PHA could improve (about 10%) both saturation and off currents. In particular, when a multilayer channel structure was adopted, the improvement became remarkable, because the underlying layers were used as a buffer layer, which could enhance the film's crystalline volume fraction. For example, under the condition of Vgs = 20 V and Vds = 20 V, a TFT with a 4-layer PHA treated nc-Si channel and a 5 nm n+ nc-Si source/drain layer could achieve the highest saturation current Isat of 5.8 × 10−6 A and the lowest Ioff of 4.1 × 10−11 A, respectively. The mechanisms related to the different factors were also discussed in detail.

Effects of the size of silicon grain on the gate-leakage current in nanocrystalline silicon thin-film transistors

The size of silicon grain in silicon thin-film transistors (TFTs) and the dependence of the gate-leakage current have been theoretically investigated after the effect of the silicon-grain size on the surface potential is considered. After the crystal-size effect has been included, the gate-leakage current of nanocrystalline silicon TFTs strongly depends on the silicon-grain size when the silicon-grain size is in the regime of nanoscale. Such a strong dependent relation results from the large changes in the band gap and dielectric constant due to size effects. The numerical calculations also demonstrate that the effect of the silicon-grain size on the gate-leakage current is independent (or weakly dependent) on the device temperature, the gate voltage, and the active-dopant density.