Nanocrystal Nonvolatile Memory Research Articles

Improved performance of Au nanocrystal nonvolatile memory by N2-plasma treatment on HfO2 blocking layer**Project supported by the High Level Talent Project of Xiamen University of Technology, China (Grant Nos. YKJ16012R and YKJ16016R) and the National Natural Science Foundation of China (Grant No. 51702271).

The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–TaN/HfO2/SiO2/p-Si are also characterized. After N2-plasma treatment, the nitrogen atoms are incorporated into HfO2 film and may passivate the oxygen vacancy states. The surface roughness of HfO2 film can also be reduced. Those improvements of HfO2 film lead to a smaller hysteresis and lower leakage current density of the MOS capacitor. The N2-plasma is introduced into Au nanocrystal (NC) nonvolatile memory to treat the HfO2 blocking layer. For the N2-plasma treated device, it shows a better retention characteristic and is twice as large in the memory window than that for the no N2-plasma treated device. It can be concluded that the N2-plasma treatment method can be applied to future nonvolatile memory applications.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices* *Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.

Investigation of p-channel and n-channel junctionless gate-all-around polycrystalline silicon nanowires with silicon nanocrystals nonvolatile memory

This work presents p-channel and n-channel junctionless (JL) polycrystalline silicon (poly-Si) nanowires gate-all-around (GAA) nonvolatile memory (NVM) devices with silicon nanocrystals charge trapping layer. Experimental results indicate that the n-channel device has better programming efficiency and p-channel device has better erasing efficiency. For p-channel device, an extrapolation of the memory window to 10 yr demonstrates that 95% of the stored charge can be retained at high temperature of 85 °C. Such the p-channel and n-channel JL-GAA NVMs are feasible for use in system-on-panel (SOP) and 3-D stacked flash memory applications.

Effects of charge storage dielectric thickness on hybrid gadolinium oxide nanocrystal and charge trapping nonvolatile memory

The characteristics of hybrid gadolinium oxide nanocrystal (Gd2O3-NC) and gadolinium oxide charge trapping (Gd2O3-CT) memories were investigated with different Gd2O3 film thickness. By performing the rapid thermal annealing on Gd2O3 films with different thickness, the Gd2O3-NCs with the diameter of 6–9 nm for charge storage, surrounded by the amorphous Gd2O3 (α-Gd2O3) layer, were formed. The α-Gd2O3 layer was considered to be the charge trapping layer, resulting in the large memory window of Gd2O3-NC/CT memories with thick Gd2O3 film. The charge trapping energy level of the Gd2O3-NCs and α-Gd2O3 layer was extracted to be 0.16 and 0.45 eV respectively by using the temperature-dependent retention measurement. Further, after a 106 program/erase cycling operation, the memory with thin Gd2O3 film can be predicted to sustain a 94% memory window of the first cycling one while the memory with thick Gd2O3 film suffered from a 30% charge loss because of the traps within the α-Gd2O3 layer. The Gd2O3 film thickness of 10 nm was optimized to exhibit superior performances of the Gd2O3-NC/CT memory, which can be applied into the nonvolatile memory.

Applications of Focus Ion Beam Technique in the Characterization of Nanocrystal Nonvolatile Memory Devices

Extended abstract of a paper presented at Microscopy and Microanalysis 2013 in Indianapolis, Indiana, USA, August 4 – August 8, 2013.

Characteristics of plasma immersion ion implantation treatment on tungsten nanocrystal nonvolatile memory

In this study, we investigate the oxygen plasma-immersion-ion-implantation (PIII) treatment on the characteristics of tungsten nanocrystal (W-NC) nonvolatile memories. The oxygen PIII has multi-species plasma of O+, O++ and O2+, and the simulation can successfully fit the oxygen secondary ion mass spectrometry (SIMS) profile. It is observed that the oxygen PIII treatment can effectively improve the disturbance effect and endurance characteristics for over 1.5V memory window under 104 program/erase cycling. The discrete W-NCs are clearly observed from the high-resolution transmission electron microscopy (HRTEM) image and confirmed by the energy-dispersive X-ray (EDX) analysis. Nevertheless, some damage of O2 PIII on tunneling oxide and silicon surface may lead to the inadequate retention characteristics. By fine-tuning the plasma ions, the PIII technique can be applied into future nonvolatile memory manufacturing.

Speed Enhancement of WSi2Nanocrystal Memory with Barrier-Engineered Si3N4/HfAlO Tunnel Layer

WSi2 nanocrystal nanofloating gate capacitors with multistacked Si3N4/HfAlO high-k tunnel layers were fabricated and their electrical properties were characterized. The thicknesses of the Si3N4 and HfAlO tunnel layers were 1.5 and 3 nm, respectively. The asymmetrical Si3N4/HfAlO tunnel layer was modulated to enhance the tunneling efficiency to improve program and erase speeds. The flat-band voltage shift of the WSi2 nanofloating gate capacitor was about 7.2 V after applied voltages swept were from -10 to 10 V and from 10 to -10 V. Then, the program/erase speeds and the memory window under programming and erasing at ±7 V were 300 µs and 1 V, respectively. As demonstrated in the results, the WSi2 nanocrystal memory with barrier-engineered Si3N4/HfAlO layers could be applied to enhance the program and erase speeds at low operating voltages for nanocrystal nonvolatile memory application.

Speed Enhancement of WSi2 Nanocrystal Memory with Barrier-Engineered Si3N4/HfAlO Tunnel Layer

WSi2 nanocrystal nanofloating gate capacitors with multistacked Si3N4/HfAlO high-k tunnel layers were fabricated and their electrical properties were characterized. The thicknesses of the Si3N4 and HfAlO tunnel layers were 1.5 and 3 nm, respectively. The asymmetrical Si3N4/HfAlO tunnel layer was modulated to enhance the tunneling efficiency to improve program and erase speeds. The flat-band voltage shift of the WSi2 nanofloating gate capacitor was about 7.2 V after applied voltages swept were from -10 to 10 V and from 10 to -10 V. Then, the program/erase speeds and the memory window under programming and erasing at ±7 V were 300 µs and 1 V, respectively. As demonstrated in the results, the WSi2 nanocrystal memory with barrier-engineered Si3N4/HfAlO layers could be applied to enhance the program and erase speeds at low operating voltages for nanocrystal nonvolatile memory application.

Low operation voltage and high thermal stability of a WSi2 nanocrystal memory device using an Al2O3/HfO2/Al2O3 tunnel layer

A WSi2 nanocrystal nonvolatile memory device was fabricated with an Al2O3/HfO2/Al2O3 (AHA) tunnel layer and its electrical characteristics were evaluated at 25, 50, 70, 100, and 125 °C. The program/erase (P/E) speed at 125 °C was approximately 500 μs under threshold voltage shifts of 1 V during voltage sweeping of 8 V/−8 V. When the applied pulse voltage was ±9 V for 1 s for the P/E conditions, the memory window at 125 °C was approximately 1.25 V after 105 s. The activation energies for the charge losses of 5%, 10%, 15%, 20%, 25%, 30%, and 35% were approximately 0.05, 0.11, 0.17, 0.21, 0.23, 0.23, and 0.23 eV, respectively. The charge loss mechanisms were direct tunneling and Pool-Frenkel emission between the WSi2 nanocrystals and the AHA barrier engineered tunneling layer. The WSi2 nanocrystal memory device with multi-stacked high-K tunnel layers showed strong potential for applications in nonvolatile memory devices.

Direct Tunneling and Storage of Electrons in Ni Nanocrystals Embedded within MOS Structure

Recently, nanocrystal nonvolatile memory (NVM) devices using nanocrystals (NCs) have attracted great research interest. In this work, we investigated the feasibility of Ni nanocrystals embedded in metal oxide semiconductor (MOS) capacitor structure for NV

A novel 2-T structure memory device using a Si nanodot for embedded application

Performance and reliability of a 2 transistor Si nanocrystal nonvolatile memory (NVM) are investigated. A good performance of the memory cell has been achieved, including a fast program/erase (P/E) speed under low voltages, an excellent data retention (maintaining for 10 years) and good endurance with a less threshold voltage shift of less than 10% after 104 P/E cycles. The data show that the device has strong potential for future embedded NVM applications.

Thermal Stability of Metal-Silicide Nanocrystal Nonvolatile Memory with Barrier Engineered Tunnel Layers

WSi2 nanocrystal nonvolatile memory devices were fabricated with a silicon oxide-nitride-oxide (SiO2: 2 nm/Si3N4:2 nm/SiO2:3 nm) tunnel layer. WSi2 nanocrystals of 2.5 nm diameters and a density of 3.6 x 10(12) cm(-2) were formed using radio frequency magnetron sputtering and annealing processes. The WSi2 nanocrystal nonvolatile memory device exhibited strong thermal stability during writing/erasing operations at temperatures up to 125 degrees C. When the writing/erasing voltages were applied at +10 V/-10 V for 500 ms, the memory window of the initial approximately 2.6 V decreased by approximately 1.1 V at 25 degrees C and 0.4 V at 125 degrees C after 10(4) sec, respectively. These results show that WSi2 nanocrystals with barrier-engineered tunnel layers are possible for application in nonvolatile memory devices.

Memory characteristics of ordered Co/Al2O3 core-shell nanocrystal arrays assembled by diblock copolymer process

An ordered Co/Al2O3 core-shell nanocrystal (NC) nonvolatile memory device was fabricated. Self-assembled diblock copolymer process aligned the NCs with uniform size. Co/Al2O3 core-shell NCs were formed using atomic layer deposition of Al2O3 before and after the ordered Co NC formation. Compared to Co NC memory, Co/Al2O3 core-shell NC memory shows improved retention performance without sacrificing writing and erasing speeds.

Improved characteristics for Pd nanocrystal memory with stacked HfAlO–SiO 2 tunnel layer

Stacked HfAlO–SiO 2 tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO 2 tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO 2 tunnel layer. Owing to the thermally induced traps in HfAlO–SiO 2 films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO 2/Pd NCs/1.5 nm-HfAlO/3.5 nm-SiO 2/Si structure. A N 2 plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO 2.

Charge loss in WSi 2 nanocrystals nonvolatile memory with SiO 2/Si 3N 4/SiO 2 tunnel layer

We have studied the charge loss in WSi 2 nanocrystals nonvolatile memory device with silicon oxide-nitride-oxide (SiO 2: 2 nm/Si 3N 4:2 nm/SiO 2: 3 nm) tunnel layer. The WSi 2 nanocrystals of 2.5 nm diameters and 3.6 × 10 12 cm −2 density were formed between tunnel and control oxide layers. When the programming/erasing voltages were applied at 10 V/−10 V during 500 ms, the memory window was measured about 2.7 V and maintained at about 1.1 V after 10 4 s at 25 °C. In this device, the activation energies for the charge loss rates from 10% to 50% in compare to an initial charge were about 0.14 eV. This charge loss could be caused by a cycling-induced oxide damage or tunnel oxide break down. Therefore, it has a feasibility of application to highly-integrate nonvolatile memory after optimize the charge loss effect by thermal stress and improve the tunnel layer stability.

Influence of hydrogen plasma treatment on charge storage characteristics in high density tungsten nanocrystal nonvolatile memory

This study focuses on the influence of a hydrogen plasma treatment on electrical properties of tungsten nanocrystal nonvolatile memory. The X-ray photon emission spectra show that, after the hydrogen plasma treatment, a change in binding energy occurs such that Six+ and Siy+ peaks appear at a position that is shifted about 2.3 and 3.3eV from Si0+ in Si 2p spectra. This indicates that Si dangling bonds are passivated to form a Si–H bond structure in the SiO2. Furthermore, the transmission electron microscopy shows cross-sectional and plane-view for the nanocrystal microstructure after the hydrogen plasma treatment. Electrical measurement analyses show improved data retention because the hydrogen plasma treatment enhances the quality of the oxide surrounding the nanocrystals. The endurance and retention properties of the memory device are improved by about 36% and 30%, respectively.

Formation and nonvolatile memory characteristics of W nanocrystals by in-situ steam generation oxidation

The authors provide the formation and memory effects of W nanocrystals nonvolatile memory in this study. The charge trapping layer of stacked a-Si and WSi 2 was deposited by low pressure chemical vapor deposition (LPCVD) and was oxidized by in-situ steam generation system to form uniform W nanocrystals embedded in SiO 2. Transmission electron microscopy analyses revealed the microstructure in the thin film and X-ray photon-emission spectra indicated the variation of chemical composition under different oxidizing conditions. Electrical measurement analyses showed the different charge storage effects because the different oxidizing conditions influence composition of trapping layer and surrounding oxide quality. Moreover, the data retention and endurance characteristics of the formed W nanocrystal memory devices were compared and studied. The results show that the reliability of the structure with 2% hydrogen and 98% oxygen at 950 °C oxidizing condition has the best performance among the samples.

Electrical Characteristics of TiSi2 Nanocrystal Nonvolatile Memory with Barrier-Engineered Tunnel Layer

In this study, we fabricated TiSi2 nanocrystal nonvolatile memory devices with silicon nitride–oxide–nitride (NON) and SiO2 tunnel barriers. The TiSi2 nanocrystals with diameters of 2–5 nm and a density of 1.5 ×1012 cm-2 were formed using radio frequency magnetron sputtering in argon and a postannealing process. The memory effect of the TiSi2 nanocrystal memory device with the NON tunnel barrier was observed at about 0.7 V at 100 ms when the applied program/erase voltages were +7 V/-7 V. Also, the memory window of the NON tunnel barrier device was maintained up to 1.3 V after 103 s. These results indicate that the NON tunnel barrier provides an effective tunneling thickness for the fast program/erase speeds and an adequate physical thickness for long charge retention characteristics in nonvolatile memory devices.

Formation of the distributed NiSiGe nanocrystals nonvolatile memory formed by rapidly annealing in N 2 and O 2 ambient

In this work, electrical characteristics of the Ge-incorporated Nickel silicide (NiSiGe) nanocrystals memory device formed by the rapidly thermal annealing in N 2 and O 2 ambient have been studied. The trapping layer was deposited by co-sputtering the NiSi 2 and Ge, simultaneously. Transmission electron microscope results indicate that the NiSiGe nanocrystals were formed obviously in both the samples. The memory devices show obvious charge-storage ability under capacitance–voltage measurement. However, it is found that the NiSiGe nanocrystals device formed by annealing in N 2 ambient has smaller memory window and better retention characteristics than in O 2 ambient. Then, related material analyses were used to confirm that the oxidized Ge elements affect the charge-storage sites and the electrical performance of the NCs memory.

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.