Nano CMOS Research Articles

Effects of non-fatal electrostatic discharge on the threshold voltage degradation in nano CMOS devices

Effects of non-fatal electrostatic discharge on the threshold voltage degradation in nano CMOS devices

Design and Analysis of an Arithmetic and Logic Unit using Single Electron Transistor

The demand for low power dissipation and increasing speed elicits numerous research efforts in the field of nano CMOS technology. The Arithmetic Logic Unit is the core of any central processing unit. In this paper, we designed a 4-bit Arithmetic and Logic Unit (ALU) using Single Electron Transistor (SET). Single-electron transistor (SET) is a new type of switching nanodevice that uses controlled single-electron tunneling to amplify the current. The single-electron transistor (SET) is highly scalable and possesses ultra-low power consumption when compared to conventional semiconductor devices. Reversible logic gates designed using SET are used for performing 4-bit arithmetic operations. We modelled symmetric single gate SET operating at room temperature using Verilog A code. The design is carried out in cadence simulation environment. The 4-bit SET based ALU design exhibits the power of 0.52 nW and delay of 350pS.

Analysis of reliability for fault tolerant design in NANO CMOS logic circuit

The emerging nano scaled electronic devices are Carbon Nanotubes (CNT), Silicon nanowires (SINW), nano CMOS switches etc. In Nano CMOS switches, the devices can be interconnected to build the nano scaled CMOS circuit. In this nano CMOS circuit, faults occur at three levels, such as gate level, circuit level and switch level. This paper focusses on the switch level faults of stuck-open or stuck-off and stuck-short or stuck-on that frequently occurs in CMOS switches. To overcome the switch level faults and to increase the reliability, the fault tolerant technique known as the Quadded Transistor (QT) structure is used. An analytical model has been formulated to determine the probability of failure by analyzing the stuck open and stuck short faults. Also, the model has been formulated by implementing QT structure for the single CMOS NAND2 gate. By the use of analytical formulations, the results has been simulated for the occurrence of minimum to maximum number of defective transistors in CMOS logic circuit.

Electrolyte-Insulator-Semiconductor pH Sensors with Arrayed Patterns Manufactured by Nano Imprint Technology

This work focuses on the sensing properties of electrolyte-insulator-semiconductor (EIS) pH sensors with arrayed patterns manufactured by integrating nano imprint technology (NIL) and CMOS process. The arrayed patterns, made of line and square at about ∼200–400nm with a width/space ratio of about ∼1/1-1/2, were fabricated by NIL; followed by the manufacturing of the EIS sensors. The patterns were studied by atomic force microscopy (AFM) and scanning electron microscopy (SEM). The sensors, with arrayed patterns, all exhibited higher sensitivity, lower hysteresis, and lower drift properties than the single one did. The effects of arrayed patterns (square or line) and pattern density on the sensing area were also investigated. With this approach, the sensors can be fabricated for future high performance biochemical sensing applications.

Effects of thermal annealing on the charge localization characteristics of HfO2/Au/HfO2 stack

To be compatible with the mainstream nano CMOS technology and to further increase the density and to reduce power consumption of non-volatile memory, high-k dielectric will become the major technology option for next generation non-volatile memory technology. To ensure the required retention time and to maintain the scalability of floating gate memory transistor, the charge store in future memory transistor should be accompanied with the high-k insolated metal or conductive clusters, islands, or nano-particles. This work proposes a simple method to fabricate high-k isolated metal cluster array. An HfO2/Au/HfO2 stack was first grown by using atomic layer deposition (ALD) and thermal evaporation, respectively, for HfO2 and Au film deposition. After a high-temperature thermal annealing, a number of HfO2-buried Au islands with diameter of about 5 to10nm were obtained. Capacitance–voltage (C–V) measurements show that the charge storage characteristics of the Au-embedded HfO2 structure were affected greatly by the annealing conditions. Depending on the annealing temperature (it should be governed by thickness of Au layer also), the thermal annealing may lead to the formation of Au islands/clusters, the improvement of HfO2 blocking property as a result of defect removal, or the deterioration of the blocking property of HfO2 due to the crystallization of HfO2 film. Process optimization should be conducted for further improving the charge localization characteristics.

Leakage current analysis for stack based Nano CMOS Digital Circuits

Due to the growing impact of subthreshold and gate leakage, static leakage is contributing more and more towards the power dissipation in deep submicron Nano CMOS technology. There have been many works on subthreshold leakage and techniques to reduce it, such as controlling the input vector to the circuit in standby mode, forcing stack and body bias control. In this tutorial paper we have reviewed the leakage current with change in drain source, gate and bulk voltages for 4 different submicron technologies using the latest PTM models. Simulation result shows the effect of gate leakage and subthreshold leakage in total leakage current for different input vectors for a stack of 3 Nano technology NMOS transistors, further analyzes also the subthreshold and total leakage variation with input vector in a stack of 4 Nano technology NMOS transistors.

Analog/mixed-signal circuit design in nano CMOS era

Analog/mixed-signal circuit design in nano CMOS era

Effects of Carbon Co-Implantation on Transient Enhanced Diffusion and Performances of the Phosphorus Doped Ultra-Shallow Junction Nano NMOSFET

The carbon (C) co-implantation and advanced flash anneal were employed to form the ultra shallow junction (USJ) for future nano CMOS technology applications. The effects of the C co-implantation process on dopant transient enhanced diffusion (TED) of the phosphorus (P) doped nano USJ NMOSFETs were investigated in details. The USJ NMOSFETs were prepared by a foundry’s 55 nano CMOS technology. Various implantation energies and doses for both C and P ions were employed. Results show the suppression of the TED is strongly dependent on both C and P implantation conditions. Besides, the mechanisms of P TED and suppression by C ion co-implantation were illustrated comprehensively with schematic models.

Foreword Special Issue on Characterization of Nano CMOS Variability by Simulation and Measurements

The five invited papers and 11 contributed papers in this special issue discuss topics such as process variation, device variability, hierarchical modeling tools, and address challenges such as device mismatch and SRAM noise margin variability.

Special issue on characterization of nano CMOS variability by simulation and measurements

Special issue on characterization of nano CMOS variability by simulation and measurements

Improvement of Thermal Stability of Nickel Silicide Using Multi-Capping Structure

In this paper, the electrical properties of NiSi have been characterized using multi capping layer structure for nano CMOS application. We have investigated the formation and thermal stability of Ni silicide using Ni, Ti and TiN capping layers (Ti/Ni/TiN) as a function of Rapid Thermal Processing (RTP) temperature. It was shown that the NiSi with multi capping layer has lower sheet resistances than that with single capping (TiN) layer. NiSi with multi capping layer also showed much better thermal stability. It was verified that the formation Ni-Ti-Si ternary like layer at the top region of thhe NiSi results in improvement of thermal stability.

Dependency of 1/f Noise on Initial Oxidation Method in Nano-CMOS Technology

In this paper, it is presented that flicker (1/f) noise of ultra thin gate oxide can be improved by initial oxidation and subsequent plasma nitridation(PN). PN which raises Nitrogen peak upward from the Si/Oxide interface to gate polysilicon/Oxide interface is adopted mainly to improve the life time such as Negative-Bias Temperature Instability (NBTI) and hot carrier in Nano CMOS technology. Three different types of initial oxidation prior to plasma nitridation are investigated. One is slow thermally grown oxide(STO) in very small Oxygen ambient, another is rapid thermally grown oxide(RTO) and the other is grown in Nitrous oxygen ambient (NO). Oxide thickness of all splits is about 14.5< Then, it is shown that STO has the lowest drain current noise power (Sid) among the splits. The interface trap densitie (Dit) of each oxide is characterized using charge pumping method. Finally, we reached a conclusion that the 1/f noise can be significantly reduced by initial STO and Plasma Nitridation in Nano CMOS technology.

Thermal Stability Enhancement of Nickel Monosilicides by Addition of Iridium

We fabricated thermal evaporated 10 nm-Ni/(poly)Si and 10 nm-Ni/1 nm-Ir/(poly)Si films to investigate the thermal stability of nickel monosilicide at the elevated temperatures by rapid annealing them at the temperatures of <TEX>$300{\sim}1200^{\circ}C$</TEX> for 40 seconds. Silicides for salicide process was formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester is used for sheet resistance. Scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An x-ray diffractometer and an auger depth profile scope were used for phase and composition analysis, respectively. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to <TEX>$1200^{\circ}C$</TEX> and <TEX>$800^{\circ}C$</TEX>, respectively, while the conventional nickel monosilicide showed low resistance below <TEX>$700^{\circ}C$</TEX>. The grain boundary diffusion and agglomeration of silicides led to lower the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.

Nano-scale CMOS를 위한 Ni-germano Silicide의 열 안정성 연구

In this paper, novel methods for improvement of thermal stability of Ni-germano Silicide were proposed for nano CMOS applications. It was shown that there happened agglomeration and abnormal oxidation in case of Ni-germano Silicide using Ni only structure. Therefore, 4 kinds of tri-layer structure, such as, Ti/Ni/TiN, Ni/Ti/TiN, Co/Ni/TiN and Ni/Co/TiN were proposed utilizing Co and Ti interlayer to improve thermal stability of Ni-germano Silicide. Ti/Ni/TiN structure showed the best improvement of thermal stability and suppression of abnormal oxidation although all kinds of structures showed improvement of sheet resistance. That is, Ti/Ni/TiN structure showed only 11 ohm/sq. in spite of 600 , 30 min post silicidation annealing while Ni-only structure show 42 ohm/sq. Therefore, Ti/Ni/TiN structure is highly promising for nano-scale CMOS technology.