NAND Logic Circuits Research Articles

Design of Universal Logic Gates using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit.

Quaternary NAND Logic and Complementary Ternary Inverter with p‐MoTe2/n‐MoS2 Heterostack Channel Transistors

AbstractApplications of 2D semiconductors have been extensively studied, much oriented to various electron devices. Recently, multivalue field‐effect transistors (FETs) are also included among 2D‐based electron device studies in consideration that multivalue FETs may resolve power consumption issues in future integrated circuits. Several n‐channel devices are thus reported along with a few p‐channel devices, while studies to achieve both n‐ and p‐channel multivalue FETs are hardly found. Here, both n‐ and p‐channel multivalue FETs are fabricated using p‐MoTe2/n‐MoS2 heterostack channel architecture, where either p‐ or n‐channel ternary value FET is reproducible by switching the stacking order of p‐ and n‐channel layer. The main ternary value mechanism originates from resonant tunneling type injection and channel inversion, which take place during device operation. For a state‐of‐the‐art device application in 2D electronics, a quaternary NAND logic circuit is for the first time demonstrated by integrating two ternary n‐channel FETs, and a complementary ternary inverter is also fabricated by integrating multivalue p‐channel and plain n‐channel FET.

Investigation of Power Consumption Effect of Various Memristor Emulators on a Logic Gate

Memristor, also known as memory resistor, is considered as the fourth passive electronic element expressing the relationship between magnetic flux and electric charge. One of the most important features of the memristor is that it has low power consumption. Minimizing power consumption is an important issue in the electronic circuits. However, the fact that the memristor element was not yet fully manufactured has led researchers to design memristor-like emulator circuits. These circuits, which approximate the memristor properties, are realized by combining the other existing electronic elements. In this paper, a basic NAND logic gate is considered and the change in power consumption when using a memristor instead of the standard resistor in the gate circuit is examined. For this purpose, the NAND logic circuit was constituted for four different memristor emulators, and the power consumption values of these circuits were obtained by simulation and experiments. These values are compared with the power consumption values of NAND circuits obtained by using standard resistors equivalent to the memristor resistance. The results clearly show that the memristor gate circuits reduce power consumption compared to standard resistive gate circuits.

Flexible, high mobility short-channel organic thin film transistors and logic circuits based on 4H\u201321DNTT

The low mobility and large contact resistance in organic thin-film transistors (OTFTs) are the two major limiting factors in the development of high-performance organic logic circuits. Here, solution-processed high-performance OTFTs and circuits are reported with a polymeric gate dielectric and 6,6 bis (trans-4-butylcyclohexyl)-dinaphtho[2,1-b:2,1-f]thieno[3,2-b]thiophene (4H–21DNTT) for the organic semiconducting layer. By optimizing and controlling the fabrication conditions, a high saturation mobility of 8.8 cm2 V−1 s−1 was demonstrated as well as large on/off ratios (> 106) for relatively short channel lengths of 15 μm and an average carrier mobility of 10.5 cm2 V−1 s−1 for long channel length OTFTs (> 50 μm). The pseudo-CMOS inverter circuit with a channel length of 15 μm exhibited sharp switching characteristics with a high signal gain of 31.5 at a supply voltage of 20 V. In addition to the inverter circuit, NAND logic circuits were further investigated, which also exhibited remarkable logic characteristics, with a high gain, an operating frequency of 5 kHz, and a short propagation delay of 22.1 μs. The uniform and reproducible performance of 4H–21DNTT OTFTs show potential for large-area, low-cost real-world applications on industry-compatible bottom-contact substrates.

Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation

The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to planar MOSFET due to increased gate voltage controllability. However, the hot carrier injection (HCI) is a serious reliability issue for nanoscale FinFET and this should be taken care for reliable circuit design. The introduction of uniaxial strain in the channel of FinFET to enhance the performance further limits the reliable design of VLSI circuits. Hence, there is a great need to capture these device-level variations in circuits through physics-based models. In this paper, one such analytical model of hot carrier (HC) degradation in uniaxial strained TG FinFET based on reaction–diffusion mechanism is developed, considering various geometrical aspects of the device, for the first time. The developed model is validated using experimentally calibrated Sentaurus TCAD simulation results. The results show that the strain in the channel worsens the degradation of threshold voltage due to HCI. The developed model is integrated in Cadence circuit simulator, and the impact of HC degradation in strained TG FinFET-based CMOS NAND logic circuit is analyzed.

Large scale MoS2 nanosheet logic circuits integrated by photolithography on glass

We demonstrate 500 × 500 μm2 large scale polygrain MoS2 nanosheets and field effect transistor (FET) circuits integrated using those nanosheets, which are initially grown on SiO2/p+–Si by chemical vapor deposition but transferred onto glass substrate to be patterned by photolithography. In fact, large scale growth of two-dimensional MoS2 and its conventional way of patterning for integrated devices have remained as one of the unresolved important issues. In the present study, we achieved maximum linear mobility of ∼9 cm2 V−1 s−1 from single-domain MoS2 FET on SiO2/p+–Si substrate and 0.5∼3.0 cm2 V−1 s−1 from large scale MoS2 sheet transferred onto glass. Such reduced mobility is attributed to the transfer process-induced wrinkles and crevices, domain boundaries, residue on MoS2, and loss of the back gate-charging effects that might exist due to SiO2/p+–Si substrate. Among 16 MoS2-based FETs, 13 devices successfully work (yield was more than 80%) producing NOT, NOR, and NAND logic circuits. Inverter (NOT gate) shows quite a high voltage gain over 12 at a supply voltage of 5 V, also displaying 60 μs switching speed in kilohertz dynamics.

Organic devices based on pentacene and perylene by the neutral cluster beam deposition method

In this study, on the basis of p-type pentacene and n-type N,N′-dioctyl-perylene-3,4,9,10-tetracarboxylic acid diimide (PTCDI-C8) organic field-effect transistors (OFETs) and two-input complementary NAND logic gates in the top-contact device configuration were produced and characterized. The organic active layers were deposited on hydroxyl-free polymethylmethacrylate (PMMA)-modified indium tin oxide (ITO) glass gate substrates by the neutral cluster beam deposition (NCBD) method. The morphological and structural properties of the organic semiconducting active layers on the PMMA substrates were examined using atomic force microscopy, X-ray diffraction and contact-angle goniometry. Based on the growth of high-quality, well-packed crystalline films on the PMMA dielectric-modified ITO gate substrates, the p- and n-type transistors exhibited hole and electron mobilities of 0.247 and 7.23×10−2cm2/Vs, respectively, in the air without encapsulation. The trap density and activation energy were also derived from the transport characteristics for the temperature dependence of the mobilities in the temperature range 20−300K for the first time. Because of the well balanced p- and n-type OFETs in the devices, the complementary metal-oxide semiconductor (CMOS) NAND logic circuits exhibited a high voltage gain and a large noise margin with slight hysteresis.

Self‐Assembled Nanodielectrics for High‐Speed, Low‐Voltage Solution‐Processed Polymer Logic Circuits

Solution‐processed polymer‐based logic circuits are typically associated with high operating voltage and slow switching speeds. Here, polymer field‐effect transistors (PFETs) fabricated on hybrid self‐assembled nanodielectric (SAND) structures are reported, the latter consisting of alternating organic–inorganic layers exhibiting low leakage current (≈10−9 A cm−2) and high capacitance (≈0.8 μF cm−2). Suitable device engineering, controllable dielectric parameters, and interface energetics enable PFET operation at ±1 V, field‐effect mobility (μ FET) > 2.0 cm2 V−1 s−1, subthreshold swing ≈100 mV dec−1, and switching response ≈150 ns. These performance parameters are orders of magnitude higher than similar devices fabricated from other polymer dielectrics. Inverter and NAND logic circuits fabricated from these SAND‐based PFETs possess voltage gain up to 38 and maximum‐frequency bandwidth of 2 MHz. A systematic study comparing different classes of dielectric and semiconducting material attributes the enhanced performance to improved relaxation dynamics of the SAND layer and tunable chemically functionalized interfaces.

P.3: 3‐D Stacked Complementary TFT Devices using n‐type α‐IGZO and p‐type F8T2 TFTs — Operation Confirmation of NOT and NAND Logic Circuits –

AbstractWe have developed 3‐D stacked complementary TFT devices using n‐type α‐IGZO and p‐type F8T2 TFTs on PET substrates. We confirmed proper I‐V characteristics of both the α‐IGZO and F8T2 TFTs and correct input‐output characteristics of both NOT and NAND logic circuits. The operation confirmation of the NAND logic circuit suggests that any advanced logic circuit can be composed using these complementary TFT devices.

A clock generator for a high-speed high-resolution pipelined A/D converter

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop (DLL), and a new differential structure is used to improve the precision of the charge pump. Meanwhile, a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition. The proposed circuit, designed by SMIC 0.18 μm 3.3 V CMOS technology, is used as a clock generator for a 14 bit 100 MS/s pipelined ADC. The simulation results have shown that the duty cycle ranged from 10% to 90% and can be adjusted. The average duty cycle error is less than 1%. The lock-time is only 13 clock cycles. The active area is 0.05 mm2 and power consumption is less than 15 mW.

NOT and NAND logic circuits composed of top-gate ZnO nanowire field-effect transistors withhigh-k Al2O3 gate layers

Electrical characteristics of NOT and NAND logic circuits fabricatedusing top-gate ZnO nanowire field-effect transistors (FETs) withhigh-k Al2O3 gate layers were investigated in this study. To form a NOT logic circuit, two identical FETs whoseIon/Ioff ratios wereas high as ∼108 were connected in series in a single ZnO nanowire channel, sharing a common sourceelectrode. Its voltage transfer characteristics exhibited an inverting operation and its logicswing was 98%. In addition, the characteristics of a NAND logic circuit composed of threetop-gate FETs connected in series in a single nanowire channel are discussed in this paper.

Impact of single pMOSFET dielectric degradation on NAND circuit performance

Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source-to-drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.

A new CMOS NAND logic circuit for reducing hot-carrier problems

The circuit, which uses a design concept called the self-bootstrapping method (SBM), lowers the channel electric field in the n-MOSFET during switching transients, leading to the suppression of the n-MOSFET substrate current. Experimental and simulation results show that about 3.9 times smaller peak substrate current is obtained in the NAND logic circuits with SBM when compared to the conventional NAND logic circuit. The circuit also gives shorter rise and fall times and better noise margin. The SBM concept provides highly reliable CMOS NAND logic without any change in device structure and/or fabrication process. >

Design and Application of Static Logic Directors

A digital computer program written by Westinghouse engineers aids the design of new static logic systems for metal mills. The computer program accepts logic equations specifying the functions to be performed. The program generates circuit drawings of logic circuitry plus paper tape for controlling an automatic wiring machine. The automatic wiring machine wires the back panel receptacles for plug-in cards which contain the integrated-circuit AND/NAND logic elements. The design engineer determines functional requirements to be performed by the logic circuits. He expresses these requirements in convenient logic statement form and adds comments on circuit functioning. Logic and comment statements are keypunched for input to the computer. The computer analyzes the equations, converts the functions to AND/ NAND logic circuits and generates the punched-paper tape required by the automatic wiring machine. In addition, the computer generates the circuit diagrams showing the actual AND/NAND circuits with complete (JIC) cross references and comments on circuit functioning. During computer processing diagnostic messages are generated to aid in finding design errors. Only one type of logic board is used in the new static logic system to perform all logic functions. This reduces maintenance to mere board replacement and greatly reduces spare board inventory. Triac outputs are featured in addition to normal contact closure outputs. Traic is a static ac switch which can operate pilot-operated solenoid valves, contactors, indicating lights, and other common ac loads. The logic system combines the advantages of fully wired integrated-circuit logic with the convenience and accuracy of computer aided design.