N-detection Test Sets Research Articles

Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift

Test sets that target standard fault models may not always be sufficient for detecting all defects. To evaluate test sets for the detection of unmodeled defects, n-detect test sets (which detect all modeled faults at least n times) have previously been proposed. Unfortunately, n-detect test sets are often prohibitively long. In this paper, we investigate the ability of shadow flip-flops connected into a MISR (Multiple Input Signature Register) to detect stuck-at faults fortuitously multiple times during scan shift. We explore which flip-flops should be shadowed to increase the value of n for the least detected stuck-at faults for each circuit studied. We then identify which circuit characteristics are most important for determining the cost of the MISR needed to achieve high values of n. For example, circuits that contain a few flip-flops with upstream fault cones that cover a large percentage of all faults in the circuit can often achieve high n-detect coverage fortuitously with a low-cost MISR. This allows a DFT engineer to predict the viability of this MISR-based approach early in the design cycle.

Test-Quality Optimization for Variable <inline-formula> <tex-math notation="TeX">$n$ </tex-math></inline-formula>-Detections of Transition Faults

Aggressive technology scaling in modern chips resulted in complicated faulty timing behaviors, which necessitate undesirable long development cycle and high test volumes to ensure product quality. To reduce the test time, cost-effective and timing-efficient test selection algorithms are used to choose optimal test inputs from a large-volume test set. In this paper, we define an approximate longest sensitized path (ALSP) metric to derive the longest sensitized path for all transition faults (TFs) from the detectability of TFs with very low computational complexity. With the ALSP metric, a general public utilities-based parallel test selection method is proposed to choose a small test set with high delay test quality from the timing-unaware n-detection test set. Our results demonstrate the comparison with a commercial automatic test pattern generation tool and a previous timing-aware test selection method targeting small delay defects, and confirm that our test selection algorithm can achieve better delay test coverage and higher n -detection fault coverage with steeper fault coverage curves of ordered patterns, for the same pattern count.

Multiple detection test generation with diversified fault partitioning paths

The dependability of current and future nanoscale technologies highly depends on the ability of the testing process to detect emerging defects that cannot be modeled traditionally. Generating test sets that detect each fault more than one times has been shown to increase the effectiveness of a test set to detect non-modeled faults, either static or dynamic. Traditional n-detect test sets guarantee to detect a modeled fault with minimum n different tests. Recent techniques examine how to quantify and maximize the difference between the various tests for a fault. The proposed methodology introduces a new systematic test generation algorithm for multiple-detect (including n-detect) test sets that increases the diversity of the fault propagation paths excited by the various tests per fault. A novel algorithm tries to identify different propagating paths (if such a path exists) for each one of the multiple (n) detections of the same fault. The proposed method can be applied to any linear, to the circuit size, static or dynamic fault model for multiple fault detections, such as the stuck-at or transition delay fault models, and avoids any path or path segment enumeration. Experimental results show the effectiveness of the approach in increasing the number of fault propagating paths when compared to traditional n-detect test sets.

Compact Test Pattern Selection for Small Delay Defect

This letter proposes an algorithm that selects a small number of test patterns for small delay defects from a large N-detect test set. This algorithm uses static upper and lower bound analysis to quickly estimate the sensitized path length so that the central processing unit (CPU) time can be reduced. By ignoring easy faults, only a partial fault dictionary, instead of a complete fault dictionary, is built for test pattern selection. Experimental results on large International Test Conference benchmark circuits show that, with very similar quality, the selected test set is 46% smaller and the CPU time is 42% faster than that of timing-aware automated test pattern generation (ATPG). With the proposed selection algorithm, small delay defect test sets are no longer very expensive to apply.

Non-Uniform Coverage by $n$-Detection Test Sets

The use of n-detection test sets increases the likelihood of defect detection. With a uniform value of for all the target faults, the expectation is that defects across the circuit will be covered uniformly. This paper demonstrates that this may not be the case by considering the four-way bridging faults detected by n-detection test sets for single stuck-at faults in benchmark circuits. Partitioning the bridging faults into subsets according to their dominated line, the results show that certain subsets have significantly lower bridging fault coverage than others. Thus, certain defect sites are significantly less covered than others. This paper also shows that it is possible to predict which subsets will have low bridging fault coverage based on the numbers of detections of single stuck-at faults under a conventional one-detection test set. This observation leads to a simplified n-detection test generation strategy. It also points to the possibility of using higher numbers of detections for certain single stuck-at faults, or targeting other fault models only at the sites that are expected to be less covered.

Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage

An n-detection test set detects each target fault n times. A higher value of n increases the likelihood that defects around the site of a target fault will be detected. However, an n -detection test set that consists of single-pattern tests (generated for single stuck-at faults) cannot guarantee that delay defects will be detected. For this it is necessary to use multi-pattern tests. The procedure described in this work generates a multi-pattern n-detection test set for single stuck-at faults. The procedure is applied starting from a single-pattern n-detection test set for single stuck-at faults. Experimental results demonstrate that the multi-pattern n-detection test set achieves a high transition fault coverage. It achieves a similar bridging fault coverage to the single-pattern test set. An added advantage is that the multi-pattern test set typically requires significantly fewer clock cycles for test application than the single-pattern test set.

Test Pattern Generation of Relaxed $n$-Detect Test Sets

While defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as multiple detect or n-detect test sets, are of increased quality for a number of common defects in deep sub-micrometer technologies. Method for multiple detect test generation usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in a multiple detect (n-detect) test set, while preserving the original fault coverage. The experimental results demonstrate that the number of specified bits in, even compact, n-detect test sets can be significantly reduced without any impact on the n-detect property. Additionally, in many cases, the size of the test set is reduced.

Embedding N-Detect Test Set into Controlled Bits Stream

N-detect testing suffers from the drawback with its test set size and test application time. A Build-In Self-Test (BIST) N-detect test patterns generation method based on controlled linear shifter is proposed, which embeds test set into the controlled bits stream and provide high defect coverage with low storage area overhead and test application time. In this method, corresponding N test patterns are generated for each fault, by using the bits which are directly stored in ROM to control the first bit of the linear shifter, dynamically generate the complete N-detect test set. Simulation results for benchmark circuits show that the proposed method with power consumption considering provides considerably lower area overhead, shorter test application time and higher transition-fault coverage compared to other recently-published methods.

Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects

This letter presents a new method to generate compact stuck-at test sets that offer high defect coverage. The proposed method first selects the most effective patterns from a large N-detect repository, by using a new output deviation-based metric. Then it embeds complete coverage of stuck-at faults within these patterns, and uses the proposed metric to further improve their defect coverage. Results show that the proposed method outperforms a recently proposed competing approach in terms of unmodeled defect coverage. In many cases, higher defect coverage is obtained even than much larger N-detect test sets for several values of N. Finally, results provide the insight that, instead of using N-detect testing with as large N as possible, it is more efficient to combine the output deviations metric with multi-detect testing to get high-quality, compact test sets.

Forward-Looking Reverse Order Fault Simulation for $n$ -Detection Test Sets

We extend the concept of forward-looking reverse order fault simulation to n-detection test sets. Forward-looking reverse order fault simulation is an efficient static test compaction process similar to reverse order fault simulation, but with the advantage that it results in test sets that do not contain any unnecessary tests. The application of test compaction procedures to n-detection test sets is important since the test sets are larger than conventional test sets. We demonstrate that forward-looking reverse order fault simulation produces smaller test sets than reverse order fault simulation and measure the quality of the resulting test sets by their bridging fault coverage.

Evolutionary derivation of optimal test sets for neural network based analog and mixed signal circuits fault diagnosis approach

Testing issues are becoming more and more important with the quick development of both digital and analog circuit industry. In this paper, we study the utilization of evolutionary algorithms for optimal input vectors derivation of neural network based analog and mixed signal circuits fault diagnosis approach and compare the results with normal method. We have introduced a new procedure which uses the n-detection test set concept and selects the input samples in a way that for each case of fault injection, there will be at least n sample to activate that fault. This procedure performs the optimization in two ways. The first one called speed method generates samples in a way that acceptable decision strength and lower training phase duration would be achieved. The second one called stamina method generates samples in a way that best decision strength and higher training phase duration would be achieved. Experimental results demonstrate that the obtained input voltages yields fault diagnosis with increased fault coverage and high decision strength.

On the Saturation of $n$-Detection Test Generation by Different Definitions With Increased $n$

An n-detection test set contains different tests for each target fault. The value of is typically determined based on test set size constraints, and certain values have become standard. Appropriate values for are investigated in this paper by considering the saturation of the n-detection test generation process. As is increased, eventually, the rate of increase in test set quality starts dropping. Saturation occurs when the increase in test set quality with drops below a certain level. Three parameters of an n-detection test set are introduced to measure the saturation of the test generation process: 1) the fraction of faults detected times or less by the test set; 2) the fraction of faults detected fewer than times by the test set; and 3) the test set size relative to the size of a one-detection test set. It is demonstrated that the behavior of each one of these parameters follows a unique pattern as is increased, and certain features of this behavior can be used to identify saturation. All the parameters can be efficiently computed during the test generation process.

Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns

At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too high; the 2005 International Roadmap for Semiconductors predicts that test-application times will be 30 times larger in 2010 than they are today. In addition, many new types of defects cannot be accurately modeled using existing fault models. Therefore, there is a need to model the quality of test patterns such that they can be quickly assessed for defect screening. Test selection is required to choose the most effective pattern sequences from large test sets. Current industry practice for test selection is based on fault grading, which is computationally expensive and must also be repeated for every fault model. Moreover, although efficient methods exist today, for fault-oriented test generation, there is a lack of understanding on how best to combine the test sets thus obtained, i.e., derive the most effective union of the individual test sets without simply taking all the patterns for each fault model. This paper presents the use of the output deviation as a surrogate coverage-metric for pattern modeling and test grading. A flexible, but general, probabilistic-fault model is used to generate a probability map for the circuit, which can subsequently be used for test-pattern reordering. The output deviations resulting from the probability map(s) are used as a coverage-metric to model test patterns; the higher the deviation, the better the quality of the test pattern. We show that, for the ISCAS benchmark circuits and as compared to other reordering methods, the proposed method provides ldquosteeperrdquo coverage curves for different fault models.

Worst-case and average-case analysis of n -detection test sets and test generation strategies

Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n because of the increase in test set size with n. Both a worst-case analysis and an average-case analysis is performed to investigate the effects of restricting n on the unmodelled fault coverage of an (arbitrary) n-detection test set of a full-scan circuit. The analysis is independent of any particular test set or any particular test generation procedure. It is based on a specific set of target faults and a specific set of untargeted faults. It shows that, depending on the circuit, very large values of n may be needed to guarantee the detection of all the untargeted faults. The implications of these results are discussed and it is also demonstrated that the proposed analysis methods can be used to evaluate the effects of incorporating into the n-detection test generation procedure specific strategies aimed at improving the n-detection test set quality.

Forming N-detection test sets without test generation

We describe a procedure for forming n -detection test sets for n >1 without applying a test generation procedure to target faults. The proposed procedure accepts a one-detection test set. It extracts test cubes for target faults from the one-detection test set, and merges the test cubes to obtain new test vectors. By extracting and merging different test cubes in different iterations of this process, an n -detection test set is obtained. Merging of test cubes does not require test generation or fault simulation. Fault simulation is required for extracting test cubes for target faults. We demonstrate that the resulting test set is as effective in detecting untargeted faults as an n -detection test set generated by a deterministic test generation procedure. We also discuss the application of the proposed procedure starting from a random test set (instead of a one-detection test set).

A measure of quality for n-detection test sets

N-detection test sets are useful in improving the coverage of unmodeled faults. We introduce a measure of quality that allows us to compare two test sets in terms of their ability to detect unmodeled faults based on the concept of n-detections. Using this measure, we describe a procedure for ordering an n-detection test set for stuck-at faults such that the quality of a test set comprised of the first K tests of the test set is as high as possible. This is useful when only K tests of the test set can be accommodated in the tester memory or to help ensure that unmodeled faults are detected as early as possible during the test application process. We present experimental results demonstrating that the proposed ordering yields test sets with increased coverage of unmodeled faults.

Exact computation of maximally dominating faults and its application to n-detection tests for full-scan circuits

The size of an n-detection test set increases approximately linearly with n. This increase in size may be too fast when an upper bound on test set size must be satisfied. A test generation method is proposed for obtaining a more gradual increase in the sizes of n-detection test sets, while still ensuring that every additional test would be useful in improving the test set quality. The method is based on the use of fault-dominance relations to identify a small subset of faults (called maximally dominating faults) whose numbers of detections are likely to have a high impact on the defect coverage of the test set. Structural analysis obtains a superset of the maximally dominating fault set. A method is proposed for determining exact sets of maximally dominating faults. New types of n-detection test sets are based on the approximate and exact sets of maximally dominating faults. The test sets are called (n,n2)-detection test sets and (n,n2,n3)-detection test sets. Experimental results demonstrate the usefulness of these test sets in producing high-quality n-detection test sets for the combinational logic of ISCAS-89 benchmark circuits.

On n-detection test sets and variable n-detection test sets for transition faults

We study the effectiveness of n-detection test sets based on transition faults in detecting defects that affect the timing behavior of a circuit. We use path delay faults as surrogates for unmodeled defects, and show that the path delay fault coverage achieved by an n-detection transition fault test set increases significantly as n is increased. We also introduce a method to reduce the number of tests included in an n-detection test set by using different values of n for different faults based on their potential effect on the defect coverage. The resulting test sets are referred to as variable n-detection test sets.

A cone-based genetic optimization procedure for test generation and its application to n-detections in combinational circuits

Test generation procedures based on genetic optimization were shown to be effective in achieving high fault coverage for benchmark circuits. In this work, we propose a representation of test patterns for genetic optimization based test generation, where subsets of inputs are considered as indivisible entities. Using this representation, crossover between two test patterns t/sub 1/ and t/sub 2/ copies all the values of each subset either from t/sub 1/ or from t/sub 2/. By keeping input subsets undivided, activation and propagation capabilities of t/sub 1/ and t/sub 2/ are expected to be captured and carried over to the new test patterns. Experimental results presented show that the proposed scheme results in complete stuck-at test sets and n-detection test sets for combinational circuits, even in cases where other procedures report incomplete fault coverages.