N-channel Metal Oxide Semiconductor Field Research Articles

Gamma-radiation Induced Degradation of the Electrical Characteristics of NMOSFETs

In this paper, we present the gamma-radiation induced degradation of the electrical characteristics of N-channel Metal Oxide Semiconductor Field Effect Transistors (NMOSFETs). The exposure was done with a 60Co gamma-ray source over the total dose range of 1 kGy to 10 kGy, with a dose rate of 3.9 kGyhr. The effects of irradiation induced degradation on device parameters such as threshold voltage, low field mobility, device transconductance (Gm), saturation drain current, off state leakage current and subthreshold swing were investigated. The threshold voltage was determined using the linear extrapolation method. The device dimensions with Wide/Long channel that excluded the Narrow Channel Effect (NCE) and the Short Channel Effect (SCE) were measured. The results showed that the threshold voltage, device transconductance and low field mobility decreased but the saturation drain current, off state leakage current and subthreshold swing increased as the gamma irradiation increased. Finally, the macro parameter models were investigated and discussed.

A Study of the Performance of an N-Channel MOSFET Under Gamma Radiation as a Dosimeter

This paper is devoted to the effect of gamma radiation on commercial IRFP250 N-channel metal oxide semiconductor field effect transistors (MOSFETs) in a dose range from 0.5 Gy up to 50 Gy. The device under investigation can be utilized for radiation therapy and dose detection and measurement. The different MOSFETs parameters such as drain current ID, threshold voltage Vth, sensitivity S, transconductance G, and annealing are studied. The main goal of this work is to accurately determine the previous parameters before and after ionizing radiation. From the obtained results, one can estimate the dosage by measuring the mentioned device parameters. The study will be of benefit not only for MOSFET applications as a dosimeter, but also for selecting the type which can tolerate this kind of radiation, especially for space and satellite applications. Finally, the annealing process is done at different temperatures and time. This will aid in determining the ability of the device under test (DUT) to recover. Therefore, the fading of the DUT is studied. From our results, the MOSFET device has excellent properties as a dosimeter. Moreover, in our case, the transconductance and sensitivity were enhanced after irradiation.

Analytical Model for Drain Current of a Ballistic MOSFET

A simplified analytical approach within the framework of Landauer-Buttiker formalism has been employed to model the drain current in a ballistic n-channel metal oxide semiconductor field effect transistor (MOSFET) and the expression for the device threshold voltage has been obtained. To achieve ballistic operation the said MOSFET has been modeled considering low temperature (77 K) and intrinsic silicon channel for electronic motion of the charge carriers. The model incorporates quantum confinement effect, drain induced barrier lowering (DIBL) and short channel effects (SCE). Further, the effects due to surface scattering and back scattering are included in this model to obtain a near ballistic behavior. The current-voltage characteristics are compared with the available experimental results and are found to be in reasonable agreement.

Extraction of the active acceptor concentration in (pseudo-) vertical GaN MOSFETs using the body-bias effect

We report and discuss the performance of an enhancement mode n-channel pseudo-vertical GaN metal oxide semiconductor field effect transistor (MOSFET). The trench gate structure of the MOSFET is uniformly covered with an Al2O3 dielectric and TiN electrode material, both deposited by atomic layer deposition (ALD). Normally-off device operation is demonstrated in the transfer characteristics. Special attention is given to the estimation of the active acceptor concentration in the Mg doped body layer of the device, which is crucial for the prediction of the threshold voltage in terms of device design. A method to estimate the electrically active dopant concentration by applying a body bias is presented. The method can be used for both pseudo-vertical and truly vertical devices.Since it does not depend on fixed charges near the channel region, this method is advantageous compared to the estimation of the active doping concentration from the absolute value of the threshold voltage.

Gamma-ray irradiation-induced mobility enhancement of 4H-SiC NMOSFETs with a Ba-silicate interface layer

4H-SiC n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with a Ba-silicate interface layer were irradiated with gamma-rays up to 850 kGy at room temperature. Above 600 kGy, the field effect mobility increased from 12 to 18 cm2 V−1 s−1. The narrower channel in the NMOSFETs enhanced radiation responses, such as mobility enhancement and threshold voltage shift. These results indicate that the edge of the channel significantly modifies the electrical characteristics.

Changes in transconductance(gm) and Ion/Ioff with high-K dielectrics in MX2 monolayer 10 nm channel double gate n-MOSFET

We investigate monolayer Transition Metal Dichalcogenides (TMDs) of type MX2 (MoS2, MoSe2, MoTe2, WS2 and WSe2) 10 nm n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) with different dielectrics (SiO2, Al2O3, HfO2 and TiO2) using DFT and NEGF formalism. Results suggest that increasing dielectric constant increases both transconductance (gm) and Ion/Ioff for all type of MX2 channels. Ion/Ioff and gm increases by one order with increase in dielectric constant K. Among all type of MX2 channels considered, WS2 channels results into highest values of gm (∼36.29 uS) and Ion/Ioff (4.3*107) with TiO2 dielectric. Variation in Subthreshold Slope (SS) with increase in dielectric constants are negligibly small, SS value of 58.52 mV/dec is obtained with Al2O3 dielectric for WS2 channel. However, a SS value of ∼60.02 mV/dec is obtained with TiO2 dielectric for all MX2 channels. The results suggest that TiO2 dielectric with WS2 channel can be used for High Performance (HP) and Low Power (LP) devices since it shows large Ion/Ioff (∼107) and SS around 60 mV/dec.

On the turn-around phenomenon in n-MOS transistors under NBTI conditions

We have experimentally analyzed negative bias temperature instability (NBTI) stress/recovery cycle on n-channel metal oxide semiconductor field effect transistors (n-MOSFET’s). Data obtained by current–voltage (I–V) and charge pumping (CP) techniques have revealed a turn-around phenomenon in both threshold voltage shift (ΔVth) and maximum CP current shift (ΔICP-Max). This allows us to separate the evolution of interface traps (permanent) and near interfacial oxide traps “border traps” (recoverable) as a function of the stress time. The ability of separation comes from the fact that interface and oxide traps induce opposite shifts in ΔVth. Contrarily to NBTI/n-MOSFET, NBTI/p-MOSFET is unable to achieve trap separation because both trap types induce shifts in the same direction. Exploiting the turn-around effect, we have been able to follow the evolution of the degradation over the stress time. NBTI stress/relaxation cycle CP measurements on n-MOSFET have shown a progressive creation of traps; starting from the interface traps to near interfacial traps. This new and simple procedure will give a deeper insight into the dynamics of traps build up under NBTI conditions.

Model of hot-carrier induced degradation in ultra-deep sub-micrometer nMOSFET

The degradation produced by hot carrier (HC) in ultra-deep sub-micron n-channel metal oxide semiconductor field effect transistor (nMOSFET) has been analyzed in this paper. The generation of negatively charged interface states is the predominant mechanism for the ultra-deep sub-micron nMOSFET. According to our lifetime model of p-channel MOFET (pMOFET) that was reported in a previous publication, a lifetime prediction model for nMOSFET is presented and the parameters in the model are extracted. For the first time, the lifetime models of nMOFET and pMOSFET are unified. In addition, the model can precisely predict the lifetime of the ultra-deep sub-micron nMOSFET and pMOSFET.

Physical understanding of different drain-induced-barrier-lowering variations in high-k/metal gate n-channel metal-oxide-semiconductor-field-effect-transistors induced by charge trapping under normal and reverse channel hot carrier stresses

In this paper, the drain induced barrier lowering (DIBL) variations in High-k/Metal gate n-channel metal–oxide–semiconductor field effect transistor under the normal and reverse channel hot carrier (CHC) stress are studied. It is found that DIBL decreases under normal CHC stress mode while increases under reverse CHC mode. The different DIBL variation under normal and reverse CHC stresses is proposed to be attributed to stress-induced charge trapping by cold carriers from the channel rather than hot carriers from the pinch off region, which can be explained by energy band bending theory.

Impact of Dynamic Stress on Reliability of Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with SiON Gate Dielectric Operating in a Complementary Metal–Oxide–Semiconductor Inverter at Elevated Temperature

This paper investigates the impact of dynamic stress on the reliability of a nanoscale n-channel metal–oxide–semiconductor field effect transistor (nMOSFET) with a SiON gate dielectric operating in a complementary metal–oxide–semiconductor (CMOS) inverter at an elevated temperature T. Experimental results indicate that the shift of threshold voltage Vth by dynamic stress is much larger than that by various static stresses in short channel nMOSFETs. Under a dynamic stress, the OFF-state stress generated interface traps and unfilled electron traps because of the OFF-state hot carrier effect due to drain induced barrier lowering (DIBL) at high T. Although the subsequent ON-state did not produce any new defects, it filled the electron traps, which increased the Vth abruptly. Consecutive application of OFF- and ON-state stresses caused a buildup of recoverable and permanent electron traps, and interface traps, thereby resulting in the significant increase in Vth. In addition, the dynamic stress degradation was frequency-independent up to 500 kHz and its impact on nMOSFET lifetime depends strongly on gate lengths. These results indicate that OFF-state induced defects are the main cause for dynamic stress degradation and can impose a significant limitation on CMOS device scaling.

Impact of Dynamic Stress on Reliability of Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with SiON Gate Dielectric Operating in a Complementary Metal–Oxide–Semiconductor Inverter at Elevated Temperature

This paper investigates the impact of dynamic stress on the reliability of a nanoscale n-channel metal–oxide–semiconductor field effect transistor (nMOSFET) with a SiON gate dielectric operating in a complementary metal–oxide–semiconductor (CMOS) inverter at an elevated temperature T. Experimental results indicate that the shift of threshold voltage Vth by dynamic stress is much larger than that by various static stresses in short channel nMOSFETs. Under a dynamic stress, the OFF-state stress generated interface traps and unfilled electron traps because of the OFF-state hot carrier effect due to drain induced barrier lowering (DIBL) at high T. Although the subsequent ON-state did not produce any new defects, it filled the electron traps, which increased the Vth abruptly. Consecutive application of OFF- and ON-state stresses caused a buildup of recoverable and permanent electron traps, and interface traps, thereby resulting in the significant increase in Vth. In addition, the dynamic stress degradation was frequency-independent up to 500 kHz and its impact on nMOSFET lifetime depends strongly on gate lengths. These results indicate that OFF-state induced defects are the main cause for dynamic stress degradation and can impose a significant limitation on CMOS device scaling.

Characterization of Hf1-xZrxO2 Gate Dielectrics with 0≤x≤1 Prepared by Atomic Layer Deposition for Metal Oxide Semiconductor Field Effect Transistor Applications

In this work, we investigated the influence of incorporating zirconia (ZrO2) in HfO2 gate dielectric on the electrical properties and reliability of n-channel metal oxide semiconductor field effect transistors (nMOSFETs). Detailed film physical, chemical and optical properties of Hf1-xZrxO2 as a function of Zr content were studied using high resolution transmission electron microscopy (HR-TEM), angle resolved X-ray photoelectron spectroscopy (AR-XPS), and spectroscopic ellipsometer (SE). Compared to HfO2, Hf1-xZrxO2 provides not only higher k values for further equivalent oxide thickness (EOT) scaling but also lower capacitance–voltage (C–V) hysteresis, lower threshold voltage (Vt) shift (ΔVt), and higher time-to-failure (TTF) lifetimes. Improved TTF lifetime of as high as three orders of magnitude and 35% lower Vt shift were achieved from the Hf1-xZrxO2 gate stack with x=0.8. The improved reliability of the Hf1-xZrxO2 gate dielectric is attributed to the reduced charge trapping in the Hf1-xZrxO2 gate dielectric caused by the ZrO2 incorporation.

Trade-Off Relationship between Si Recess and Defect Density Formed by Plasma-Induced Damage in Planar Metal–Oxide–Semiconductor Field-Effect Transistors and the Optimization Methodology

Physical damage induced by high-energy ion bombardment during plasma processing is characterized from the viewpoint of the relationship between surface-damaged layer (silicon loss) and defect site underneath the surface. Parameters for plasma-induced damage (PID), Si recess depth (dR) and residual (areal) defect density after wet-etch treatment (Ndam), are calculated on the basis of a modified range theory, and the trade-off relationship between dR and Ndam is presented. We also model their effects on device parameters such as off-state leakage (Ioff) and drain saturation current (Ion) of n-channel metal–oxide–semiconductor field effect transistors (MOSFETs). Based on the models, we clarify the relationship among plasma process parameters (ion energy and ion flux), dR, Ndam, Ioff, and Ion. Then we propose a methodology optimizing ion energy and ion flux under the constraints defined by device specifications Ioff and Ion, via dR and Ndam. This procedure is regarded as so-called optimization problems. The proposed methodology is applicable to optimizing plasma parameters that minimize degradation of MOSFET performance by PID.

Trade-Off Relationship between Si Recess and Defect Density Formed by Plasma-Induced Damage in Planar Metal–Oxide–Semiconductor Field-Effect Transistors and the Optimization Methodology

Physical damage induced by high-energy ion bombardment during plasma processing is characterized from the viewpoint of the relationship between surface-damaged layer (silicon loss) and defect site underneath the surface. Parameters for plasma-induced damage (PID), Si recess depth (dR) and residual (areal) defect density after wet-etch treatment (Ndam), are calculated on the basis of a modified range theory, and the trade-off relationship between dR and Ndam is presented. We also model their effects on device parameters such as off-state leakage (Ioff) and drain saturation current (Ion) of n-channel metal–oxide–semiconductor field effect transistors (MOSFETs). Based on the models, we clarify the relationship among plasma process parameters (ion energy and ion flux), dR, Ndam, Ioff, and Ion. Then we propose a methodology optimizing ion energy and ion flux under the constraints defined by device specifications Ioff and Ion, via dR and Ndam. This procedure is regarded as so-called optimization problems. The proposed methodology is applicable to optimizing plasma parameters that minimize degradation of MOSFET performance by PID.

A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology

A MOS-NDR (negative differential resistance) transistor which is composed of four n-channel metal–oxide–semiconductor field effect transistors (nMOSFETs) is fabricated in standard 0.35 μm CMOS technology. This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD (resonant tunneling diode) in current–voltage characteristics. At the same time it can realize a modulation effect by the third terminal. Based on the MOS-NDR transistor, a flexible logic circuit is realized in this work, which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor. It turns out that MOS-NDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.

Characterization of fast charge trapping in bias temperature instability in metal-oxide-semiconductor field effect transistor with high dielectric constant

We used pulse bias temperature instability measurements to investigate the energy distributions of fast charge trapping sources to understand the origin of fast charge traps in an HfO2 device. The trap energy level was extracted using a trap-to-band tunneling model by changing the measurement delay time. The fast electron traps in an n-channel metal oxide semiconductor field effect transistors (MOSFET) exist in a 1 eV range below the bottom of the HfO2 conduction band. In the case of a p-channel MOSFET, the fast hole traps exist in the range 1–2 eV above the top of the HfO2 valence band, which could be attributed to a formation of negatively charged NO defects.

Investigation of Enhanced Impact Ionization in Uniaxially Strained Si n-Channel Metal Oxide Semiconductor Field Effect Transistor

The impact ionization rate in uniaxially strained silicon is evaluated from viewpoints of the ionization threshold β and maximum electric field Em for the first time. Strain and temperature dependences of β are investigated on the basis of the change in slope in a universal relation while Em, which is also dependent on strain and temperature, is investigated on the basis of the change in saturation voltage VDSAT. The impact ionization rate is a function of β and Em such that we also evaluated strain and temperature dependence of multiplication factor M - 1 (= Isub/ID) to determine the major concern of change in impact ionization rate. The result shows that the change in Em due to the change in potential drop along the channel is the major concern in a uniaxially strained silicon n-channel metal oxide semiconductor field effect transistor (nMOSFET).

An Efficient Quantum-Based Model for the Threshold Voltage of Thin Film Double Gate/Silicon on Insulator Silicon Metal Oxide Semiconductor Field Effect Transistors

In this paper, an efficient non-iterative approach for calculating the threshold voltage of nanoscale double gate n-channel metal oxide semiconductor field effect transistor (nMOSFET) is presented. First, it is shown that the parabolic potential is a reasonable approximation for the body potential along the coordinate normal to the interfaces at the threshold of conduction. Then, the eigen functions and eigen values of confined carriers are determined by solving the Schrödinger's equation using the Wentzel–Kramers–Brillouin (WKB) approximation. All the coefficients of the potential polynomial are obtained analytically at the threshold condition. To assess the accuracy of the proposed model, its predictions have been compared to the results of a numerical simulator and a previously published model. It is observed that the approach can accurately yet efficiently predict the threshold voltage for both symmetric and asymmetric double gate structures as well as fully depleted silicon on insulator (SOI) structures with intrinsic or doped body.

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and Vh degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.

Self-Aligned Asymmetric Metal–Oxide–Semiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator

We have fabricated the sub-30 nm asymmetric n-channel metal–oxide–semiconductor field effect transistors (NMOSFETs) and investigated its operation and characteristics. In this work, two key ideas are newly introduced in order to improve the device performance. One is the introduction of silicon-on-insulator (SOI) substrate to remove junction leakage paths. The other is the modification of mask layout for performance optimization and mass production. By using SOI substrate and modifying mask layout, the ON/OFF current ratio of the fabricated device is quite increased when we compared with the previous work because the source/drain junction leakage and parasitic current are suppressed. Moreover, the fabricated device has excellent scaling properties in terms of short channel effect.