N-channel Insulated Gate Bipolar Transistor Research Articles

Compensation of p-type doping in Al-doped 4H-SiC

One of the major challenges of 4H-silicon carbide (4H-SiC) is that the preparation of low resistivity p-type 4H-SiC single crystals lags seriously behind that of low resistivity n-type 4H-SiC single crystals, hindering the development of important 4H-SiC power devices such as n-channel insulated gate bipolar transistors. In particular, the resistivity of p-type 4H-SiC single crystals prepared through the physical vapor transport technique can only be lowered to around 100 mΩ cm. One of the key causes is the incomplete ionization of the p-type dopant Al with an ionization energy ∼0.23 eV. Another factor is the compensating effect. It cannot simply assume nitrogen (N) is the sole compensatory center, since the number of the compensating center is larger than the concentration of N doping. In this work, we systematically investigate the compensation of native defects and self-compensation in Al-doped 4H-SiC. It is found that the positively charged carbon vacancies (VC2+) are also the dominant compensating centers in Al-doped 4H-SiC. When the Al concentration is in the range of 1016–1019 cm−3, the concentration of holes is lower by one order of magnitude than the Al concentration because of the compensation of VC2+. As the Al concentration exceeds 1020 cm−3, the concentration of holes is only in the order of magnitude of 1019 cm−3 owing to the dominant compensation of VC2+ and supplementary self-compensation of interstitial Al (Ali3+). We propose that the passivation of VC2+ as well as quenching is effective to enhance the hole concentration of Al-doped 4H-SiC.

Fabrication of 4H-SiC n-channel IGBTs with ultra high blocking voltage

Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices, n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications. In this paper, backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs. The thickness of a drift layer was 120 μm, which was designed for a blocking voltage of 13 kV. The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V, with a differential specific on-resistance of 140 mΩ·cm2.

Epitaxial growth and characterization of thick multi-layer 4H-SiC for very high-voltage insulated gate bipolar transistors

Techniques to fabricate thick multi-layer 4H-SiC epitaxial wafers were studied for very high-voltage p- and n-channel insulated gate bipolar transistors (IGBTs). Multi-layer epitaxial growth, including a thick p− drift layer (∼180 μm), was performed on a 4H-SiC n+ substrate to form a p-IGBT structure. For an n-IGBT structure, an inverted growth process was employed, in which a thick n− drift layer (∼180 μm) and a thick p++ injector layer (>55 μm) were epitaxially grown. The epitaxial growth conditions were modified to attain a low defect density, a low doping concentration, and a long carrier lifetime in the drift layers. Reduction of the forward voltage drop was attempted by using carrier lifetime enhancement processes, specifically, carbon ion implantation/annealing and thermal oxidation/annealing or hydrogen annealing. Simple PiN diodes were fabricated to demonstrate the effective conductivity modulation in the thick drift layers. The forward voltage drops of the PiN diodes with the p- and n-IGBT structures promise to obtain the extremely low-loss and very high-voltage IGBTs. The change in wafer shape during the processing of the very thick multi-layer 4H-SiC is also discussed.

Fabrication and Performance of 16-kV Ultrahigh-Voltage SiC Power Devices

For the realization of a low-carbon-emission society and in terms of energy security, the grid connections of electric power systems are highly desired by applying a smart grid and high voltage DC transmission systems (HVDC). If switching devices with a break down voltage (BV) greater than 10kV are realized, it would be extremely beneficial for the reduction in size and loss of the power electronics components such as a loop power controller (LPC), a static synchronous compensator (STATCOM), and an intelligent solid state transformer (SST). Silicon carbide (SiC) is expected to be a next-generation power semiconductor material because its band gap is three times larger than that of Si. The breakdown electric field of SiC is 10 times higher than that of Si, allowing the thickness of the drift layer in SiC power devices to be 1/10 that of Si power devices. Thus, if an insulated-gate bipolar transistor (IGBT) structure of SiC is used, it will be possible to realize more than 10 kV MOS-controlled switching devices with very low on-resistance [1, 2].We have been working on a SiC p-channel IGBT with a BV of 10 kV [4] as well as a PiN diode with a BV of 13 kV [5]. For these devices, a high-quality n++ substrate could be used for device fabrication. However, the crystal quality of the p++ SiC substrate for the purpose of fabricating an n-channel IGBT is currently very poor with a high micropipe density and high resistivity using it as a collector. Moreover, the channel mobility for a SiC-MOSFET is still very low compared with that of a Si-MOSFET because of its 10-times higher interface-state density (Dit).To solve these problems related to n-channel SiC-IGBTs, we employed a heavily doped epitaxial p++ layer as a substrate and an implantation and epitaxial MOSFET (IEMOSFET) [5, 6] as a MOSFET structure, which is called a flip-type IE-IGBT. For the substrate, we attempted to fabricate a flip-type wafer utilizing a p++ epitaxial layer as a substrate [1]. First, a 150-mm-thick n–-type drift layer was grown on the Si-face n++ substrate after a buffer layer was formed. After the p+ collector layer was grown, the p++ substrate layer was grown to a thickness greater than 200 µm. Then, we removed the n++ substrate, turned the substrate over, and polished the surface using the CMP process. To overcome the low channel mobility of the SiC-MOSFETs, we proposed the IEMOSFET utilizing the 4H-SiC (000-1) carbon face, which has a high channel mobility greater than 100 cm2/(Vs) [6]. The bottom and top of the p-well of the IE-MOSFET are formed by ion implantation and epitaxial growth, respectively. The smooth surface of the top of the p-well enables high channel mobility. A TCAD simulation was employed to optimize the design of the active area and edge termination to obtain a low forward-voltage drop (Vf) and an ultrahigh breakdown voltage. As a result, we successfully fabricated an IE-IGBT with a low Vf of 5.0 V at 100 A/cm2 with a BV greater than 16 kV [7]. At the same time, we achieved good threshold voltage (Vth) stability and a low current-density dependence on the temperature. An ultrahigh-voltage power module was assembled to evaluate the dynamic behavior of the IE-IGBT and consisted of a tungsten base plate, a DBC base with Si3N4on it, and a copper electrode. The dynamic switching performance of the combination of the ultrahigh-voltage IE-IGBT and PiN diode will be presented.[1] X. Wang, J. A. Cooper, IEEE Transactions on Electron Devices Vol. 57, No. 2, pp. 511-515, (2010)[2] S. H. Ryu, L. Cheng, S. Dhar, C. Capell, C. Jonas, J. Clayton, M. Donofrio, M. J. O’Loughlin, A. A. Burk, A. K. Agarwal, J. W. Palmour, Materials Science Forum Vols. 717-720, p. 1135 (2012)[3] S. Katakami, H. Fujisawa, K. Takenaka, H. Ishimori, S. Takasu, M. Okamoto, M. Arai, Y. Yonezawa, K. Fukuda, Materials Science Forum Vols. 740-742, p. 958 (2013)[4] D. Okamoto, Y. Tanaka, N. Matsumoto, M. Mizukami, C. Ota, K. Takao, K. Fukuda, H. Okumura, Materials Science Forum Vols. 740-742, p. 907 (2013)[5] K. Fukuda, M. Kato, J. Senzaki, K. Kojima, Appl. Phys. Lett. Vol. 84 p. 2088 (2004)[6] S. Harada, M. Kato, K. Suzuki, M. Okamoto, T. Yatsuo, K. Fukuda, K. Arai, Technical Digest of IEDM p. 903, (2006)[7] Y. Yonezawa et al., “Low Vf and highly reliable 16 kV ultrahigh voltage SiC flip-type n-channel implantation and epitaxial IGBT”, in Proceedings of International Electron Devices Meeting (IEDM), 2013, pp. 6.6.1–6.6.4.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

High-Voltage n-Channel IGBTs on Free-Standing 4H-SiC Epilayers

In this paper, we describe a process for fabricating high-voltage n-channel double-diffused metal-oxide-semiconductor insulated gate bipolar transistors (IGBTs) on free-standing 4H silicon carbide (SiC) epilayers. In this process, all critical layers are epitaxially grown in a continuous sequence. The substrate is then removed, and device fabrication takes place on the carbon face of a free-standing epilayer having a total thickness of about 180 ?m. For a drift layer with doping and thickness values capable of blocking 20 kV, the n-channel IGBT carries 27.3-A/cm2 current at a power dissipation of 300 W/cm2, with a differential on-resistance of 177 m?·cm2. To our knowledge, this is the first detailed report of device fabrication on free-standing SiC epilayers.

Physical CAD Model for High-Voltage IGBTs Based on Lumped-Charge Approach

A new insulated gate bipolar transistor (IGBT) model developed on a physical basis is presented. The Lumped-Charge method has been revised in order to point out a more general methodology for implementing the model into a circuit form. As an example, a version of the model for the popular PSPICE simulator is presented. The N-channel IGBT structure is described by means of an evolution of the PSPICE level-1 metal oxide semiconductor field effect transistor model. An accurate mobility model has been included to precisely predict the voltage drop in the ON state. Simulation results agree well with the experiments both in static and in switching operations. The comparison between the proposed and the native IGBT PSPICE model shows the better behavior of the former. The reasons for this result have been verified by means of two-dimensional MEDICI simulations. Moreover, the proposed model is able to predict the device behavior also in critical operations like its latchup during a turn-off under short-circuit conditions.

Cell design modifications to harden an N-channel power IGBT against single event latchup

A device simulator is used to analyze the heavy ion induced failure mechanism in insulated gate bipolar transistors (IGBTs) and to investigate hardening solutions. Single event latchup was already identified as the failure mechanism. Lateral and vertical modifications of the P/sup +/ plug are proposed to reduce the efficiency of the parasitic thyristor, responsible for the latchup, and validated by 2D-simulations on a N-channel IGBT cell structure.

Numerical analysis of short-circuit safe operating area for p-channel and n-channel IGBTs

The mechanisms of destructive failure of an insulated gate bipolar transistor (IGBT) at short-circuit state are discussed. Results from two-dimensional numerical simulation of p-channel and n-channel IGBTs are presented. It is found that there are two types of destructive failure mechanisms: a secondary breakdown and a latchup. Which type is dominant in p-channel and n-channel IGBTs depends on an absolute value of forward voltage mod V/sub CE/ mod . At moderately low mod V/sub CE/ mod , the p-channel IGBT is destroyed by secondary breakdown, and the n-channel IGBT, by latchup. This is due to the difference of a type of flowing carrier crossing a base-collector junction of wide base transistor and ionization rates of electrons and holes. >