N-bit Analog-to-digital Converter Research Articles

Using Novel One-Bit ADC to Design n-Bit ADC

This work presents two novel styles for designing n-bit analog to digital converter (ADC). Each of the proposed ADCs is built using novel one-bit cell. The novel cell produces single output bit as a response to an input voltage, in addition, it outputs another analog voltage. The generated analog voltage is used again as an input to the to generate one more bit, and new analog voltage, and so on. The proposed n-bit ADC is built using the novel one-bit cell in two different styles. One design style, by connecting n ADC cells together to construct n-bit ADC that produces parallel binary outputs. The other design style realizes the n-bit ADC using single ADC cell and outputs n-bit serially. In both ADC designs introduced in this work, modularity was the main design parameter. The two different n-bit ADCs have been simulated. The first n-bit ADC with parallel outputs produces clean outputs at 50MS/s, and the other ADC design shows clean serial bits at 5KS/s.

Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices

Current-induced domain wall (DW) motion in spintronic racetrack memory promises energy-efficient analog computation using compact magnetic nanowires. This paper explores the feasibility of analog-to-digital converter (ADC) based on current-induced DW motion and introduces an n-bit ADC using n racetrack magnetic nanowires. With each magnetic nanowire having a different configuration granularity, an n-bit binary or gray code is generated simultaneously. The proposed ADC structure achieves 21 fJ/conversion-step at 20 MHz with an area of about $10~\mu \text{m}^{2}$ . The racetrack ADC is suitable for applications requiring dense ADC arrays, such as image sensors. This paper describes one ultrahigh speed digital pixel sensor imaging system benefiting from the racetrack ADC.

A Flash ADC Tolerant to High Offset Voltage Comparators

A conventional flash analog-to-digital converter (ADC) with a Wallace tree encoder ensures monotonicity and avoids missing codes, but still requires comparators with low offset voltage, which implies high area and power consumption. In this paper, we extend the purpose of this flash implementation, to allow the comparators to have extremely high offset voltages. This leads to a new approach toward the design of a flash ADC that does not require any type of calibration, allow easy porting among technologies and benefits from scaling. A statistical study is presented to demonstrate the effectiveness of the new method, and a modification is proposed to ensure full-range operation. It is shown that a proposed N-bit ADC has a performance equivalent to an $$(N-m)$$(N-m)-bit conventional flash ADC, with considerable gains in area and power consumption, with less design effort. The design flow of the OST ADC, with the necessary steps, is presented. A circuit, employing minimum dimension transistors, was fabricated in 0.13-$${\upmu }\hbox {m}$$μm CMOS and used as a proof of concept for the ADCs proposed here.

Analog-to-digital converter based on single-electron tunneling transistors

A novel single-electron tunneling transistors (SETTs) based analog-to-digital converter (ADC) is proposed in this paper. The scheme we propose fully utilizes Coulomb oscillation effect, can properly operate at T>0 K, and only a capacitive divider (built with 2n-2 capacitors) and n pairs of complementary SETTs are required for an n-bit ADC implementation. When compared with other state-of-the-art SET based ADCs our method provides the most compact solution measured in terms of circuit elements and has a potential advantage in terms of conversion speed. To illustrate the operation of the proposed scheme, a 4-bit ADC is demonstrated at 10K by means of simulation.

Single-Electron Tunneling Transistor Implementation of Periodic Symmetric Functions

This paper investigates the implementation of generic periodic symmetric functions (PSFs) with single-electron tunneling transistors (SETTs). The PSF implementation scheme we propose fully utilizes the SETT Coulomb oscillation effect and can properly operate at T>0K, and only a pair of complementary SETTs is required for the implementation of any PSF. Based on the novel PSF block, we propose an analog-to-digital converter (ADC) scheme that requires n PSFs for an n-bit ADC implementation. To demonstrate our approach, a 4-b ADC and a 7|3 counter were designed and verified at 10 K by means of simulation.

Demonstration of an optoelectronic 4-bit analog-to-digital converter using a thyristor smart comparator

An optoelectronic analog-to-digital converter (ADC) approach with 4-bit operation is demonstrated based on the combination of HFETs and an optoelectronic thyristor. The optoelectronic thyristor implements the comparator function and generates both optical digital and electrical output. The basic comparator function is combined with HFET differential amplifiers to form a smart comparator (SC) which becomes a building block that may be cascaded N times to form an N-bit ADC. In this paper, one SC is used in a feedback loop with the appropriate clocking to achieve 4-bit operation. When the optoelectronic thyristor and the HFET amplifiers are fabricated as a monolithic integrated circuit, multi-GB/s operation is expected.

Improving the resolution of selected ADCs

A technique of increasing the resolution of the counter ramp ADC (analog-to-digital converter) and successive approximation ADC without affecting their speed of operation is proposed. An n-bit simultaneous ADC is used with another m-bit successive approximation ADC or counter-type ADC to realize an (m+n)-bit ADC having the same speed of operation as an m-bit ADC.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>