Multistage Switch Architectures Research Articles

Overcoming the Switching Bottlenecks in Wavelength-Routing, Multicast-Enabled Architectures

Modular optical switch architectures combining wavelength routing based on arrayed waveguide grating (AWG) devices and multicasting based on star couplers hold promise for flexibly addressing the exponentially growing traffic demands in a cost- and power-efficient fashion. In a default switching scenario, an input port of the AWG is connected to an output port via a single wavelength. This can severely limit the capacity between broadcast domains, resulting in interdomain traffic switching bottlenecks. An unexplored solution to this issue is to exploit multiple AWG free spectral ranges (FSRs), i.e., to set up multiple parallel connections between each pair of broadcast domains. In this paper, we study, for the first time, the influence of the FSR count on the throughput of a multistage switching architecture and propose a generic and novel analytical framework to estimate the blocking probability. We assess the accuracy of our analytical results via Monte Carlo simulations. Our study points to significant improvements with a moderate increase in the number of FSRs. We show that an FSR count beyond four results in diminishing returns. Furthermore, to investigate the tradeoffs between the network- and physical-layer effects, we conduct a cross-layer analysis, taking into account pulse amplitude modulation and rate-adaptive forward error correction. We illustrate how the effective bit rate per port increases with an increase in the number of FSRs.

Cross-Point Comparison of Multistage Non-Blocking Technologies

Multistage switching networks play important role in communication and computer network. They make communication nodes connect to each other. In computer hardware switches connect processors and memories. Initially, switches are arranged as one stage interconnection. As clients are growing, multistage is a must. The finding Clos multistage switching initiated multistage technologies. Benes improves Clos by reducing number of cross-points by using a 2 x 2 switch element and call re-routing. Batcher improves the technology by other way which is sorting destination address. Banyan is then joined to Batcher to simplify routing control. This paper analyses the number of cross-point required in Clos, Benes and Batcher Banyan to accomplish multistage switching architecture of 16, 64, 256, 1024 and 2048 input/output ports. As results, Clos cross-point is in averages 495.24% higher than Benes and 160.30% higher than Batcher Banyan. Clos blocking probabilities are closed to zero. Benes blocking probabilities are conditionally zero. Batcher Banyan blocking probabilities are zero.

Scaling Limits of MEMS Beam-Steering Switches for Data Center Networks

Transparent optical circuit switching can improve the aggregate bandwidth, scalability, and cost of data center networks provided, it can meet the performance requirements on switching speed, port count, and optical efficiency. Here, we examine the theoretical scaling limits of transparent nonblocking optical switches based on MEMS electrostatic tilt mirror devices. Using physical optics and electromechanics, we present a first principles analysis of how the response speeds of a set of canonical devices scale as a function of switch port count, crosstalk, and insertion loss. Our model indicates that the optimal actuator design (parallel plate versus vertically offset comb) and actuation method (digital versus analog) changes as a function of switch port count. It also suggests that conventional switch topologies do not allow a favorable tradeoff between switching speed and optical efficiency or crosstalk. However, high switching speeds can be achieved by multistage switch architectures such as the two examples we describe, a multiport wavelength switch and a wavelength-independent space switch.

Modeling and optimization of a special multistage star switching (SMSSS) system with SEs at unequal port rates

There has been lack of an efficient design and evaluation method for the multistage star switching (MSSS) architecture in which the ports' rates of each switching element (SE) are unequal. Thus, we identify and propose a special MSSS (SMSSS) model for the first time, where all special SEs, known as basic switching modules (BSMs), are connected hierarchically into a tree profile. Unlike the existing investigations, each BSM in this model is characterized by one high-rate port and several low-rate ports. This study focuses on the analysis, design and optimization of the SMSSS model. Moreover, we propose a novel BSM cost model which relates to its flux factor considered rarely in existing studies. Two examples are demonstrated to obtain the optimal structure parameters of the SMSSS system with a minimum overall cost. The comparison of the proposed SMSSS with similar fat tree structures indicates its relative advantages.

Multistage Shared-Per-Wavelength Optical Packet Switch: Heuristic Scheduling Algorithm and Performance

This paper describes an optical switch architecture based on the shared-per-wavelength strategy for contention resolution in the wavelength domain. This strategy impacts on wavelength converters requirements and switch organization, by allowing to obtain cost saving. The general sharing concept is first introduced and the related practical solution as a multistage switch architecture is presented and thoroughly analyzed in terms of performance, control and cost perspectives. Heuristic scheduling to manage packet forwarding in a synchronous context is developed and discussed in terms of computational complexity. A simple accurate analytical model is developed and validated against simulation to numerically evaluate packet loss performance of the shared-per-wavelength switch. The main achievement of the work is represented by the proposal of a feasible approach which leads to remarkable cost saving in terms of optical gates and wavelength converters under the conditions outlined.

Multicast Connection Capacity of WDM Switching Networks With Limited Wavelength Conversion

Currently, many bandwidth-intensive applications require multicast services for efficiency purposes. In particular, as wavelength division multiplexing (WDM) technique emerges as a promising solution to meet the rapidly growing demands on bandwidth in present communication networks, supporting multicast at the WDM layer becomes an important yet challenging issue. In this paper, we introduce a systematic approach to analyzing the multicast connection capacity of WDM switching networks with limited wavelength conversion. We focus on the practical all-optical limited wavelength conversion with a small conversion degree d (e.g., d = 2 or 3), where an incoming wavelength can be switched to one of the d outgoing wavelengths. We then compare the multicast performance of the network with limited wavelength conversion to that of no wavelength conversion and full wavelength conversion. Our results demonstrate that limited wavelength conversion with small conversion degrees provides a considerable fraction of the performance improvement obtained by full wavelength conversion over no wavelength conversion. We also present an economical multistage switching architecture for limited wavelength conversion. Our results indicate that the multistage switching architecture along with limited wavelength conversion of small degrees is a cost-effective design for WDM multicast switching networks.

Large modular expandable optical switching matrices

Large optical switching matrices can be assembled incrementally from identical modules by means of a rearrangement of the Clos architecture that we have labeled SKOL. The design retains the strict-sense nonblocking properties of the Clos design, identical units provide economies of manufacture, and there are also cost advantages associated with the incremental expandability. SKOL modules can be constructed in ways that do not map back to the Clos original. In this form, SKOL is a new multistage switching architecture that is well adapted for construction with integrated optical technologies. We anticipate that the SKOL design can provide the very large, expandable optical switching matrices now demanded for optical networks.

Polarization-controlled multistage switch based on polarization-selective computer-generated holograms

We describe a polarization-controlled free-space optical multistage interconnection network based on polarization-selective computer-generated holograms: optical elements that are capable of imposing arbitrary, independent phase functions on horizontally and vertically polarized monochromatic light. We investigate the design of a novel nonblocking space-division photonic switch architecture. The multistage-switch architecture uses a fan-out stage, a single stage of 2 x 2 switching elements, and a fan-in stage. The architecture is compatible with several control strategies that use 1 x 2 and 2 x 2 polarization-controlled switches to route the input light beams. One application of the switch is in a passive optical network in which data is optically transmitted through the switch with a time-of-flight delay but without optical-to-electrical conversions at each stage. We have built and characterized a proof-of-principle 4 x 4 free-space switching network using three cascaded stages of arrayed birefringent computer-generated holographic elements. Data modulated at 20 MHz/channel were transmitted through the network to demonstrate transparent operation.

Self-routing multistage switch with repeated contention resolution algorithm for B-ISDN

In this paper, a multistage switching architecture and an efficient contention resolution algorithm are proposed for B-ISDN. The key idea is to provide abundant paths between each input-output pair and multiple access points for each output. The proposed contention resolution algorithm reduces the internal contention drastically because it allows the cells to contend repeatedly in the switching fabric. The primary features of the proposed switch are their modularity and self-routing property. Analysis results show that the proposed switch can be easily engineered to have a low cell loss probability by increasing the capacity of the input queue.

Design and performance of Multinet switch: a multistage ATM switch architecture with partially shared buffers

A new ATM switch architecture is presented. Our proposed Multinet switch is a self-routing multistage switch with partially shared internal buffers capable of achieving 100% throughput under uniform traffic. Although it provides incoming ATM cells with multiple paths, the cell sequence is maintained throughout the switch fabric thus eliminating the out-of-order cell sequence problem. Cells contending for the same output addresses are buffered internally according to a partially shared queueing discipline. In a partially shared queueing scheme, buffers are partially shared to accommodate bursty traffic and to limit the performance degradation that may occur in a completely shared system where a small number of calls may hog the entire buffer space unfairly. Although the hardware complexity in terms of number of crosspoints is similar to that of input queueing switches, the Multinet switch has throughput and delay performance similar to output queueing switches.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Comparison of buffering strategies for asymmetric packet switch modules

The performance of a class of asymmetric packet switch modules with channel grouping is analyzed. The switch module considered has n inputs and m outputs. A packet destined for a particular output address (out of g) needs to access only one of the r available physical output ports: m=gr. These switch modules are the key building blocks in many large multistage switch architectures. The focus is on the performance of input-buffered and output-buffered switch modules under geometrically bursty traffic. A combination of exact derivation, numerical analysis, and simulation yields the saturation throughput of input-buffered switch modules and the mean delay of the input-buffered and output-buffered switch modules. Tables and formulas useful for traffic engineering are presented. The results show that increasing the number of output ports per output address (r) can significantly improve switch performance, especially when traffic is bursty. Although output-buffered switch modules have significantly better performance than input-buffered switch modules when there are equal numbers of input and output ports, this performance difference becomes significantly smaller when the switch dimensions are asymmetric.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>