Multiprocessor Interconnection Research Articles

Communication performance and vertex-transitivity on folded locally twisted cube

ABSTRACT The communication performance and symmetry properties are two vital properties for a multiprocessor interconnection network. Diameter is an important factor to determine the communication performance of a graph. In a vertex-transitive graph, every vertex is identical to every other vertex in relation to its location. In this paper, we study the communication performance and vertex-transitivity property of the folded locally twisted cube . We find that the diameter of is , which is less than the diameter proposed by Peng [S. Peng, C. Guo, B. Yang, Topological properties of folded locally twisted cubes, Journal of Computational Information Systems, 11 (2015) 7667–7676]. And we prove that is vertex-transitive for n = 2, and is not vertex-transitive for .

Fault Tolerant Addressing Scheme for Oxide Interconnection Networks

The symmetry of an interconnection network plays a key role in defining the functioning of a system involving multiprocessors where thousands of processor-memory pairs known as processing nodes are connected. Addressing the processing nodes helps to create efficient routing and broadcasting algorithms for the multiprocessor interconnection networks. Oxide interconnection networks are extracted from the silicate networks having applications in multiprocessor systems due to their symmetry, smaller diameter, connectivity and simplicity of structure, and a constant number of links per node with the increasing size of the network can avoid overloading of nodes. The fault tolerant partition basis assigns unique addresses to each processing node in terms of distances (hops) from the other subnets in the network which work in the presence of faults. In this manuscript, the partition and fault tolerant partition resolvability of oxide interconnection networks have been studied which include single oxide chain networks (SOXCN), rhombus oxide networks (RHOXN) and regular triangulene oxide networks (RTOXN). Further, an application of fault tolerant partition basis in case of region-based routing in the networks is included.

Performance Analysis of Interconnection Networks Using a Novel Metric

Multiprocessor is a handling device within any event with two preparing units sharing the access. The primary reason for employing the multiprocessor includes dealing with undertakings during a consistent way while as yet supporting the framework's performance. Interconnection Networks are hub to hub associations produced using single processor or a gaggle of processing units. These connections permit data to be moved from one processor to resulting or from memory to processor, permitting the errand to be isolated and assessed similarly. Hypercube frameworks are a sort of device topography that connects various processing units with the memory modules and correctly course the data. Hypercubes are frequently seen as a chart with hubs and edges, with every hub including a processing unit and each link addressing a relation among the processing units to send information. In this paper, a bunch of multiprocessor interconnection network designs are thought of and their performance is assessed with the help of a totally extraordinary proposed metric. The normal upsides of the boundaries like diameter, degree, speed, inclusion of hubs, and loss of packets at that point on are considered to arrive at the proposed metric "Performance Index" with the help of a legitimized weight metric. Non-linear regression system is utilized to assess the exact upsides of the performance index of different multiprocessor hypercube interconnection networks. These qualities are contrasted with a summary of the productive variation reasonable for a wide choice of multiprocessing applications.

On- and Off-chip Signaling and Synchronization Methods in Electrical Interconnects

Advances in integrated circuit (IC) fabrication technology, coupled with aggressive circuit design, have led to an exponential growth in speed and integration levels. However, to improve overall system performance, the communication speed between on-chip subsystems and between ICs in printed circuit board must increase accordingly. Currently, communication bus links in various applications approach Gbps (gigabits per second) data rates. These applications include high-speed network switching, local area network, memory buses, and multiprocessor interconnection networks. In this article, we analyze the most common (popular) CMOS implementations of high speed on- and off-chip links (electrical interconnects) and show that the links’ performance should continue to scale with technology. In addition, we point to the fact that global electrical interconnects are widely acknowledged as a limiting factor in future on-chip and off-chip designs. Novel electrical interconnect driving techniques like multi-level multi-wire signaling, and GALS synchronization method primarily intended to improve performance of on-chip electrical interconnects, has been shortly analyzed. In the future, in order to handle the electrical interconnects’ finite bandwidth (data rate higher than 100 Gbps), however, more sophisticated signaling and synchronization methods will be required.

Construction and analysis of graph models for multiprocessor interconnection networks

A graph G can serve as a model for the Multiprocessor Interconnection Networks (MINs) in which the vertices represent the processors, while the edges represent connections between processors. This paper presents several graphs that could qualify as models for efficient MINs based on the small values of the graph tightness previously introduced by Cvetkovic and Davidovic in 2008. These graphs are constructed using some well-known and widely used graph operations. The tightness values of these graphs range from O(4?N) to O(?N), where N is the order of the graph under consideration. Also, two new graph tightness values, namely Third type mixed tightness t3(G) and Second type of Structural tightness t4(G) are defined in this paper. It has been shown that these tightness types are easier to calculate than the others for the considered graphs. Moreover, their values are significantly smaller.

Connectivity and Matching Preclusion for Leaf-Sort Graphs

A multiprocessor system and interconnection network have a underlying topology, which is usually presented by a graph, where nodes represent processors and links represent communication links between processors. The (conditional) matching preclusion number of a graph is the minimum number of edges whose deletion leaves the resulting graph (with no isolated vertices) that has neither perfect matchings nor almost perfect matchings. In this paper, we prove that (1) the connectivity (edge connectivity) of the leaf-sort graph CFn is [Formula: see text] for odd n and [Formula: see text] for even n; (2) CFn is super edge-connected; (3) the matching preclusion number of CFn is [Formula: see text] for odd n and [Formula: see text] for even n; (4) the conditional matching preclusion number of CFn is 3n – 5 for odd n and n ≥ 3, and 3n – 6 for even n and n ≥ 4.

A SIMULATION MODEL FOR THE PERFORMANCE EVALUATION OF HYBRID INTERCONNECTION ARCHITECTURES

Efficient scheduling of tasks in multiprocessor interconnection networks is of primary importance for parallel execution. In this paper a new scheduling algorithm that schedules the tasks on different networks of processors is proposed and evaluated. The objective is the effective utilization of resource (processors) to execute tasks of an application. Processor networks have been used in the form of different topologies. We consider a new class of architecture known as linearly extensible multiprocessor networks which are best suited with lesser number of processors. Performance of different multiprocessor networks with the proposed algorithm as well as with other standard scheduling algorithms is evaluated in terms of performance parameters namely load balance error and execution time. Simulation results show that the linear architectures achieve better performance with the proposed scheduling scheme as compared to other considered scheduling algorithms.

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4

The POWER9TM family of chips is fabricated in 14-nm silicon-on-insulator finFET technology using 17 levels of copper interconnect. The 695-mm2 24-core microprocessor features a new core based on an execution slice microarchitecture. The chip contains 8 billion transistors and has 120 MB of eDRAM L3 cache. The processor features an adaptive clock strategy to reduce timing margin needed during power supply droop events by embedding analog voltage-droop monitors that direct a digital phase-locked loop to immediately reduce clock frequency in response to a droop event. The scale-out chip IO subsystem supports up to 300-GB/s accelerator bandwidth using new 25-Gb/s links, 48 lanes of PCIeGen4 totaling 192 GB/s, eight ports of 2667 MT/s DDR4, and 256 GB/s of symmetric multiprocessor (SMP) interconnect. The scale-up chip adds additional SMP bandwidth and replaces the DDR4 memory interface with eight ports of differential memory interfaces with 230 GB/s of bandwidth resulting in 12.9 Tb/s of total off-chip bandwidth.

A Load Balancing Strategy with Migration Cost for Independent Batch of Tasks (BoT) on Heterogeneous Multiprocessor Interconnection Networks

In high performance computing, heterogeneous Multiprocessor Interconnection Networks (MINs) are used for processing of compute intensive applications. These applications are distributed on the heterogeneous computational processors of MINs arranged in specific geometrical shape. MINs are also used for transfer task between two processors in a heterogeneous multistage network for better load balancing. Load balancing algorithm plays a vital role in interconnection network in order to minimize the load imbalance on the processors. In this paper, a Load Balancing Strategy with Migration cost (LBSM) is proposed to execute an independent batch of tasks on various heterogeneous MINs viz. MetaCube, X-Torus and Folded Crossed Cube having the objective of minimizing the load imbalance on processors. In simulation study, LBSM is compared with its previous work DLBS and superior performance is shown with the considered parameters under study. Further, the performance analysis of LBSM has been conducted on MetaCube, X-Torus and Folded Crossed Cube and results have been reported accordingly.

Various Approaches for Dynamic Load Balancing for Multiprocessor Interconnection Network

Various Approaches for Dynamic Load Balancing for Multiprocessor Interconnection Network

Dynamic Scheduling Algorithm for Variants of Hypercube Interconnection Networks

Objectives: Topropose analgorithm for better performance interms of scheduling and the network usage is economical. Method/Statistical Analysis: The dynamic task scheduling algorithm has been proposed for scheduling the load on numerous cube based multiprocessor interconnection networks. Especially the efficiency of the proposed algorithm is examined in terms of performance parameters for instance Load Imbalance Factor’s as well as Execution Time for cube based multiprocessor networks; Nevertheless, a comparison is created with other standard scheduling algorithm. Findings:The comparative simulation study shows that the proposed algorithm gives better performance in terms of task scheduling on various cube based multiprocessor networks. Application: The study in such a direction implies that the variety of processors in folded hypercube has been decreased thus minimizing the cost as well as intricacy of the network without reducing the efficiency of the network. Therefore, a combination of scalable folded hypercube architecture and efficient proposed algorithm is a better organization model that supports variety of informatics applications.

Performance analysis of dynamic load balancing algorithm for multiprocessor interconnection network

Summary Multiprocessor interconnection network have become powerful parallel computing system for real-time applications. Nowadays the many researchers posses studies on the dynamic load balancing in multiprocessor system. Load balancing is the method of dividing the total load among the processors of the distributed system to progress task's response time as well as resource utilization whereas ignoring a condition where few processors are overloaded or underloaded or moderately loaded. However, in dynamic load balancing algorithm presumes no priori information about behaviour of tasks or the global state of the system. There are numerous issues while designing an efficient dynamic load balancing algorithm that involves utilization of system, amount of information transferred among processors, selection of tasks for migration, load evaluation, comparison of load levels and many more. This paper enlightens the performance analysis on dynamic load balancing strategy (DLBS) algorithm, used for hypercube network in multiprocessor system.

Properties and Performance of Cube-Based Multiprocessor Architectures

Parallel architectures provide the possibility of solving highly computational parallel applications in a variety of ways. Numerous interconnection topologies have been designed to achieve the desired performance. Nevertheless, the actual performance is far below the expectation of users when executing parallel applications on a particular multiprocessor network. This paper presents the performance study on a special class of parallel architectures known as cube based multiprocessor architectures. It describes the issues and challenges related to the design of cube-based architectures. The issues related to the design of highly parallel system such as scalability, complexity of the system and mapping of parallel application on to it are discussed. Furthermore, the problem of routing between nodes has been analyzed along with the topological properties of cube-based architectures. Simulation results are obtained by applying task scheduling algorithm on various multiprocessor networks. The comparative study implies the various aspects while designing an efficient multiprocessor interconnection network with optimal scheduling algorithm.

Some new models for multiprocessor interconnection networks

A multiprocessor system can be modeled by a graph G. The vertices of G correspond to processors while edges represent links between processors. To find suitable models for multiprocessor interconnection networks (briefly MINs), one can apply tools and techniques of spectral graph theory. In this paper, we extend some of the existing results and present several graphs which could serve as models for efficient MINs based on the small values of the previously introduced graph tightness. These examples of possible MINs arise as a result of some well-known and widely used graph operations. We also examine the suitability of strongly regular graphs (briefly SRGs) to model MINs, and prove the uniqueness of some of them.

Efficiency Measurement for Effective Stress Management in Heterogeneous 2-D Mesh Processor

Multi-Processor interconnection with varying speed is a great attempt in massive parallel processors. Such types of distributed cluster along with heterogeneous behavior will requires vast amount of scheduling efforts. Complexity increases as scheduler has to detect dynamic characteristics of the processors. Parallel schedulers are implemented in cluster technology for job assignment and placement. Further, core processor technology will provide a greater endeavor for load balancing. This research covers heterogeneous multiprocessors with 2-D mesh interconnection mapped to cube oriented memory mesh for job allocation and distribution. The job distribution will be based upon processor cycle speed. A two dimensional job slice is build, which in later stages along with many other slices overlapped to exhibit memory cube. General Terms Heterogeneous Processor Mesh, Memory Slice, Scheduling, Workload Distribution, Efficiency Degradation.

Using Transmission Lines for Global On-Chip Communication

The growing number of cores in chip multiprocessors increases the importance of interconnection for overall system performance and energy efficiency. Compared to traditional distributed shared-memory architectures, chip-multiprocessors (CMPs) offer a different set of design constraints and opportunities. As a result, a conventional packet-relay multiprocessor interconnect architecture is a valid, but not necessarily optimal, design point. Worsening wire delays, energy-inefficient routers, and the decreased importance of in-field scalability, make the conventional packet-switched network-on-chip a less attractive option. An alternative solution uses well-engineered transmission lines as communication links. These transmission lines, along with simple, practical circuits using modern complementary metal-oxide-semiconductor technology, can provide low latency, low energy, high throughput channels which can be used as a shared-medium point-to-point link. The design of the transmission lines and transceiver circuits has important architectural impact. This paper includes a first-step design effort for these components, particularly when used for a globally shared-medium bus. For medium-scale CMPs, this interconnect backbone can eliminate the need for packet switching and provide energy, as well as performance benefits when compared to a conventional mesh interconnect. We will provide a design of such a system from the ground up, including design of the transmission lines, transceiver circuits, and a simple, yet effective, architectural design for a shared-medium interconnect, and show that such a design can be a compelling alternative to packet-switched networks for CMPs.

Two Round Scheduling (TRS) Scheme for Linearly Extensible Multiprocessor Systems

the computational load over multiprocessor networks is an important problem in massively parallel systems. The key advantage of such systems is to allow concurrent execution of workload characterized by computation units known as processes or tasks. The scheduling problem is to maintain a balanced execution of all the tasks among the various available processors (nodes) in a multiprocessor network. This paper studies the scheduling of tasks on a pool of identical nodes which are connected through some interconnection network. A novel dynamic scheduling scheme named as Two Round Scheduling (TRS) scheme has been proposed and implemented for scheduling the load on various multiprocessor interconnection networks. In particular, the performance of the proposed scheme is evaluated for linearly extensible multiprocessor systems, however, a comparison is also made with other standard existing multiprocessor systems. The TRS operates in two steps to make the network fully balanced. The performance of this scheme is evaluated in terms of the performance index called Load Imbalance Factor (LIF), which represents the deviation of load among processors and the balancing time for different types of loads. The comparative simulation study shows that the proposed TRS scheme gives better performance in terms of task scheduling on various linearly extensible multiprocessor networks for both uniform and non- uniform types of loads.

Cell-Based Broadcasting Algorithms in Mobile Ad-Hoc Networks

This paper proposes new cell-based broadcasting algorithms (CBB) for mobile ad-hoc networks (MANETs). It shows how communication methods originally designed for wired multiprocessor interconnection networks can be used in MANETs. CBB algorithms are based on a logical 2-dimensional grid view of the geographical region of the MANET. They make use of existing spanning trees in the 2dimensional grid interconnection networks to support broadcasting in MANETs. In this study we developed a simulation model to measure the delivery ratio and the number of rebroadcast messages and compare the results with the well known probabilistic broadcasting algorithm.

STH: A highly scalable and economical topology for massively parallel systems

Highly parallel systems are receiving significant attention to solve the large and complex problems. This has resulted in the emergence of many attractive interconnection network topologies. This paper introduces a new processor interconnection topology called STH (Scalable Twisted Hypercube) to counter the poor scalability of twisted hypercube. Its suitability for use as multiprocessor interconnection networks has also been explored. The various properties of the proposed topology have been analyzed and it has been compared with some other highly scalable topologies of interest on a number of interconnection networks evaluation parameters. With reduced diameter, better average distance, low traffic density, low cost, maximum number of links, high bisection width and tremendous scalability, STH is more suitable for Massively Parallel Systems. Procedures for routing and broadcasting on the proposed topology have also been discussed and a simple routing algorithm has been presented. The proposed interconnection network provides a great architectural support for parallel computing due to the concurrent existence of multiple LST(m) and TQn.

A case for globally shared-medium on-chip interconnect

As microprocessor chips integrate a growing number of cores, the issue of interconnection becomes more important for overall system performance and efficiency. Compared to traditional distributed shared-memory architecture, chip-multiprocessors offer a different set of design constraints and opportunities. As a result, a conventional packet-relay multiprocessor interconnect architecture is a valid, but not necessarily optimal, design point. For example, the advantage of off-the-shelf interconnect and the in-field scalability of the interconnect are less important in a chip-multiprocessor. On the other hand, even with worsening wire delays,packet switching represents a non-trivial component of overall latency. In this paper, we show that with straight forward optimizations, the traffic between different cores can be kept relatively low. This in turn allows simple shared-medium interconnects to be built using communication circuits driving transmission lines. This architecture offers extremely low latencies and can support a large number of cores without the need for packet switching, eliminating costly routers.