Multiprocessor Board Research Articles

The COMPASS RICH-1 read-out system

This paper describes the reconfigurable read-out system for the 82944 RICH-1 channels of the COMPASS experiment (NA58) at CERN. The system is based on 192 identical large front-end boards (BORA board). BORA was designed for acquiring, digitizing, threshold subtracting and transmitting event data. The overall operation of the board is controlled and supervised by a DSP tightly interacting with an FPGA that acts as a parallel co-processor. The DSP allows characterizing each analog channel by locally calculating noise and pedestal. Each BORA communicates with the outside world through two optical fibers and through a dedicated DSP network. One optical fiber is used to receive event triggers, and the other one is used to transmit event data to subsequent processing stages of the acquisition system. The DSP network allows reconfiguring and reprogramming the DSPs and FPGAs as well as acquiring sample events to visualize the overall operation of the system. The whole RICH has eight DSP networks working in parallel. These networks are handled by DOLINA, a PC resident multiprocessor board containing eight DSPs. Each network is formed by 24 BORA DSPs and 1 DOLINA DSP. The read-out system can steadily work up to a trigger rate of 75 kHz with maximum pixel occupancy of 20%, reaching a transmission data rate of 5.13 Gbytes/s.

A fast, dataflow-oriented preprocessor for cluster counting

One of the main problems in the use of cluster counting for particle identification in high energy physics is the huge primary data rate. By means of an online data reduction system, this data rate can be reduced to the amount known from conventional integral charge/time readout. For tests and optimization of online data reduction algorithms, a RISC-based, data-flow-oriented multiprocessor board has been designed.

Multiple digital signal processor environment for intelligent signal processing

We describe a novel, expandable, multiple digital signal processor (DSP) architecture with a symbolic processing host. A multiprocessor board, called Odyssey, based on this architecture has been developed to combine symbolic and real-time digital signal processing in a single computing environment. Some of the key features of the board are: 20 million multiply/accumulates per second, 512K bytes of data space, and expandability to 16 boards on a NuBus host. The DSPs used are the TMS32020 signal processing chips developed by Texas Instruments, and the host is Texas Instruments' Explorer, a LISP machine workstation. This provides environment to perform many intelligent signal processing tasks by associating meaningful relationships between quantitative (signal processing) and qualitative (symbolic processing) entities to develop inferences using expert system technology. Applications such as grammar-driven connected speech recognition, neural network simulation, EEG analysis, and generation of speech from general English text with natural language processing are some of the tasks that can utilize the computational power of the multiple DSP and/or the associated symbolic processing capabilities. Software development tools to implement applications include the device driver to facilitate communication between the host processor and the Odyssey board, a unique window-based debugger resident on the Explorer that allows for simultaneous state display of all the processors on the board, a FORTH interpreter for high-level language programming, and a cross-assembler/linker for assembly level programming.