Multiplication Instructions Research Articles

Teaching Multiplication Based on Realistic Mathematics Education to Students at Risk of Mathematics Learning Difficulties

This study aimed to develop, implement, and evaluate an RME-supported instructional design for primary school students with MLD risk who had difficulty in multiplication at the third-grade level. In this study, a design-based research method was utilized since it was aimed to apply and assess the RME-supported instructional design to primary school students with MLD risk. The study selected the participants from primary school students with mathematics learning difficulties who had difficulty in number concepts and operations with natural numbers at the third-grade level. Participant students were determined using the criterion sampling method. As data collection tools, the Numbers and Operations Mathematics Achievement Test (NOMAT), Learning Disabilities Symptom Screening Test, curriculum-based assessment, interview, and researcher diary were used. The content analysis method was used to analyze the data obtained from qualitative data collection tools. Descriptive statistics methods were used to analyze the data obtained from quantitative data collection tools. The data obtained from the research are presented under three themes: findings on analysis, design, and development, findings on implementation, and findings on evaluation. The research results show that teaching with RME-supported instructional design is effective in students' multiplication instruction and contributes to their permanent learning.

Design and Implementation of RISC-V Based Pipelined Multiplier

Among the many microprocessors, RISC-V as an open-source instruction set is gradually gaining popularity among academia and industry. The performance of the multiplier in the microprocessor imposes constraints on the computational power of the processor. In order to improve the efficiency of multiplication instructions, a pipeline multiplier is implemented in this paper. Firstly, the partial product is generated using the Radix-4 booth. Secondly, the Wallace tree structure is used to accelerate the compression of the partial product. Then, a parallel prefix adder is used to calculate the resulting partial product to improve the timing. Finally, registers are added as a pipeline to achieve a high-efficiency multiplication calculation. With the operating voltage and temperature set to typical conditions, the integrated multiplier area is 50260.6 μm2, and the power consumption is 20.41 mW. The final frequency of the multiplier is 1 GHz in gate-level simulation.

Using Multiple Representations to Foster Multiplicative Reasoning in Students With Mathematics Learning Disabilities

Developing and supporting understanding of the meaning of multiplication and multiplicative relationships in students with mathematics learning disabilities requires carefully designed instruction that emphasizes strategic representation use. This article discusses three ways in which teachers can incorporate multiple representations within multiplication instruction to develop a deep understanding of underlying mathematical structures. First, it is important to select concrete and semi-concrete representations (e.g., discrete objects and those that illustrate continuous quantities as length or area) that will help students most accurately model the multiplication or division concept or procedure. Next, provide students with multiple representations that are presented concurrently within the same lesson so that they can make connections among the different types of representations. Last, teachers can support students to use and connect representations through mathematical discourse that elicits student thinking by not only structuring tasks around three processes, reversibility, flexibility, and generalization, but also by posing questions to elicit different ways that students can communicate their ideas using accurate and precise vocabulary.

Faster multiplication over $${\mathbb {F}}_2[X]$$ using AVX512 instruction set and VPCLMULQDQ instruction

Code-based cryptography is one of the main propositions for the post-quantum cryptographic context, and several protocols of this kind have been submitted on the NIST platform. Among them, BIKE and HQC are part of the five alternate candidates selected in the third round of the NIST standardization process in the KEM category. These two schemes make use of multiplication of large polynomials over binary rings, and due to the polynomial size (from 10,000 to 60,000 bits), this operation is one of the costliest during key generation, encapsulation, or decapsulation mechanisms. In BIKE-2, there is also a polynomial inversion which is time-consuming and this problem has been addressed in Drucker (Fast polynomial inversion for post quantum QC-MDPC cryptography, 2020). In this work, we revisit the different existing constant-time algorithms for arbitrary polynomial multiplication. We explore the different Karatsuba and Toom–Cook constructions in order to determine the best combinations for each polynomial degree range, in the context of AVX2 and AVX512 instruction sets. This leads to different kernels and constructions in each case. In particular, in the context of AVX512, we use the VPCLMULQDQ instruction, which is a vectorized binary polynomial multiplication instruction. This instruction deals with up to four polynomial (of degree up to 63) multiplications, that is four operand pairs of 64-bit words with 128-bit word storing each result, the four results being stored in one single 512-bit word. This allows to divide by roughly 3 the retired instruction number of the operation in comparison with the AVX2 instruction set implementations, while the speedup is up to 39% in terms of processor clock cycles. These results are different than the ones estimated in Drucker (Fast multiplication of binary polynomials with the forthcoming vectorized vpclmulqdq instruction, 2018). To illustrate the benefit of the new VPCLMULQDQ instruction, we used the HQC code to evaluate our approaches. When implemented in the HQC protocol, for the security levels 128, 192, and 256, our approaches provide up to 12% speedup, for key pair generation.

Approximate multiplication in young children prior to multiplication instruction

Prior work indicates that children have an untrained ability to approximately calculate using their approximate number system (ANS). For example, children can mentally double or halve a large array of discrete objects. Here, we asked whether children can perform a true multiplication operation, flexibly attending to both the multiplier and multiplicand, prior to formal multiplication instruction. We presented 5- to 8-year-olds with nonsymbolic multiplicands (dot arrays) or symbolic multiplicands (Arabic numerals) ranging from 2 to 12 and with nonsymbolic multipliers ranging from 2 to 8. Children compared each imagined product with a visible comparison quantity. Children performed with above-chance accuracy on both nonsymbolic and symbolic approximate multiplication, and their performance was dependent on the ratio between the imagined product and the comparison target. Children who could not solve any single-digit symbolic multiplication equations (e.g., 2 × 3) on a basic math test were nevertheless successful on both our approximate multiplication tasks, indicating that children have an intuitive sense of multiplication that emerges independent of formal instruction about symbolic multiplication. Nonsymbolic multiplication performance mediated the relation between children’s Weber fraction and symbolic math abilities, suggesting a pathway by which the ANS contributes to children’s emerging symbolic math competence. These findings may inform future educational interventions that allow children to use their basic arithmetic intuition as a scaffold to facilitate symbolic math learning.

Implementation of a 32 – bit RISC processor with floating point unit in FPGA platform

With the ever-growing trends in the latest technologies, digital signal processing is one of the known platforms which is used for many applications. RISC processor is the main element in all high-speed digital signal processing applications. The aim is to develop a RISC processor by including a single precision floating point unit in the instruction set along with other instructions and a complex multiplication instruction as it is commonly used in the DSP application. The floating-point unit is written according to the IEEE 754 standard and to introduce Vedic mathematics concept to compare and estimate the performance in terms of delay. The idea is to provide an optimized floating-point arithmetic unit and thereby provide an additional feature for the RISC processor instruction set. By using the Vedic multiplier, the delay is reduced by 55% compared to the normal array multiplier. The entire design is coded in Verilog HDL simulated on Xilinx ISE 14.7 platform.

A Rolling Hash Algorithm and the Implementation to LZ4 Data Compression

LZ77 is a dictionary compression algorithm by replacing the repeating sequence with the addresses of the previous referenced data in the stream. To find out these repetition, the LZ77 encoder maintains a hashing table, which have to frequently calculate hash values during the encoding process. In this paper, we present a class of rolling hash functions, that can calculate multiple hash values via a carry-less multiplication instruction. Then the proposed hash function is implemented in LZ4, which is a derivative of LZ77. The simulation shows that the encoding throughput of LZ4 has 15.7% improvement in average, and the compression ratio is ±1% in most cases.

TF-Net

Deep Neural Networks (DNNs) have become an essential component of various applications. While today’s DNNs are mainly restricted to cloud services, network connectivity, energy, and data privacy problems make it important to support efficient DNN computation on low-cost, low-power processors like microcontrollers. However, due to the constrained computation resources, it is challenging to execute large DNN models on microcontrollers. Using sub-byte low-precision input activations and weights is a typical method to reduce DNN computation. But on byte-addressable microcontrollers, the sub-byte computation is not well supported. The sub-byte inputs and weights need to be unpacked from bitstreams before computation, which incurs significant computation and energy overhead. In this paper, we propose the TF-Net pipeline to efficiently deploy sub-byte DNNs on microcontrollers. While TF-Net allows for a range of weight and input precision, we find Ternary weights and Four-bit inputs provide the optimal balance between model accuracy, computation performance, and energy efficiency. TF-Net first includes a training framework for sub-byte low-precision DNN models. Two algorithms are then introduced to accelerate the trained models. The first, direct buffer convolution, amortizes unpacking overhead by caching unpacked inputs. The second, packed sub-byte multiply-accumulate, utilizes a single multiplication instruction to perform multiple sub-byte multiply-accumulate computations. To further accelerate DNN computation, we propose two instructions, Multiply-Shift-Accumulate and Unpack, to extend the existing microcontroller instruction set. On the tested networks, TF-Net can help improve the computation performance and energy efficiency by 1.83× and 2.28× on average, respectively.

Using the Concrete–Representational–Abstract Sequence to Teach Conceptual Understanding of Basic Multiplication and Division

To meet increasingly complex mathematics standards in late elementary school, students must conceptually understand and be fluent in the operations of multiplication and division. This includes understanding the operations’ inverse relation. The purpose of the study was to investigate the effects of alternating concrete–representational–abstract (CRA) multiplication and division instruction on students’ mastery of unknown facts and on their conceptual understanding. Fourth through sixth-grade students with learning disabilities who had failed to master all multiplication facts participated in the study. The researchers used a mixed method design, measuring accuracy and fluency of facts with a multiple probe across students design and qualitative methods to capture changes in students’ explanations of their computation. The researchers demonstrated a functional relation between CRA instruction and accuracy and fluency in multiplication and division. Qualitative results indicated differences in students’ understanding of the operations. Implications of the results will be discussed further.

Examining Incremental Rehearsal: Multiplication Fluency with Fifth-Grade Students with Math IEP Goals

Reports show that only 40% of 4th-grade students are proficient in math and American students are failing to demonstrate proficiency in key areas of mathematics (National Center for Educational Statistics 2011). Improving students’ fluency of basic math multiplication facts has been recommended as a way to increase math proficiency (Psychology in the Schools, 47:342–353, 2010). Incremental rehearsal is one promising strategy for improving multiplication skills. In this study, three 5th-grade students with disabilities who had Individual Education Plan math goals received one-to-one multiplication instruction using an incremental rehearsal strategy twice per week for 7 weeks. Data indicated immediate and large effects with intervention and growth rates for each student that exceeded expectations. Implications are discussed including the importance of considering both statistically significant and instructionally meaningful results in interpretation.

Faster 64-bit universal hashing using carry-less multiplications

Intel and AMD support the Carry-less Multiplication (CLMUL) instruction set in their x64 processors. We use CLMUL to implement an almost universal 64-bit hash family (CLHASH). We compare this new family with what might be the fastest almost universal family on x64 processors (VHASH). We find that CLHASH is at least 60% faster. We also compare CLHASH with a popular hash function designed for speed (Google's CityHash). We find that CLHASH is 40% faster than CityHash on inputs larger than 64 bytes and just as fast otherwise.

Software methods for fast hashing

The carry-less multiplication instruction, PCLMULQDQ, is a relatively recent addition to the x86-64 instructions set. It multiplies two binary polynomials of degree , using arithmetic, and produces a polynomial of degree , stored in a -bit register. PCLMULQDQ is intended to speed up computations in , which are used for AES-GCM authenticated encryption. We show here how PCLMULQDQ can be used for efficient software implementation of a -bit hash function that has a low collision probability. While a -bit hash is normally not a meaningful security primitive, the discussed hashing algorithm can be leveraged for other usages that enjoy fast hashing, e.g., querying/maintaining databases. On the latest Intel architecture (Codename Broadwell), our hash function can process messages at the rate of cycles per byte.

Strongly Universal String Hashing is Fast

We present fast strongly universal string hashing families: they can process data at a rate of 0.2 CPU cycle per byte. Maybe surprisingly, we find that these families---though they require a large buffer of random numbers---are often faster than popular hash functions with weaker theoretical guarantees. Moreover, conventional wisdom is that hash functions with fewer multiplications are faster. Yet we find that they may fail to be faster due to operation pipelining. We present experimental results on several processors including low-powered processors. Our tests include hash functions designed for processors with the Carry-Less Multiplication (CLMUL) instruction set. We also prove, using accessible proofs, the strong universality of our families.

Fast inversion algorithm in GF(2m) suitable for implementation with a polynomial multiply instruction on GF(2)

The authors propose a fast inversion algorithm in Galois field GF(2m). In this algorithm, the operations required in several contiguous iterations of a previously reported algorithm based on the extended Euclid's algorithm are represented as a matrix. These operations are performed at once through the matrix by means of a polynomial multiply instruction on GF(2). When the word size of a processor is 32 or 64 and m is larger than 233 for National Institute of Standards and Technology (NIST)-recommended irreducible polynomials, the proposed algorithm computes inversion with less polynomial multiply instructions on GF(2) and exclusive-OR instructions required by previously reported inversion algorithms on an average.

Signed multiplication technique by means of unsigned multiply instruction

The present work aims at proposing an efficient technique for signed binary multiplication using unsigned, multiply instruction. Numerous examples are provided to show efficiency of the proposed approach in the context of practical software implementation. Performance of the technique is compared to the software emulated versions of classical methods, such as radix-2 Booth method, reversal of sign method (negative to positive conversion) and sign extension method. The proposed algorithm is suitable for embedded systems which are based on widespread microprocessors/microcontrollers which have an unsigned multiplication in their instruction set but no signed multiply instruction. The algorithm includes only one unsigned multiplication and two subtractions. Various samples of code presenting the signed multiplication are provided in the assembly language for an MCS-51 compatible microcontroller. The comparison of the performance of algorithm is carried out for classical MCS-51 core and innovative AT89LPx core treated as a reference microcontroller.

Speeding scalar multiplication over binary elliptic curves using the new carry-less multiplication instruction

The availability of a new carry-less multiplication instruction in the latest Intel desktop processors significantly accelerates multiplication in binary fields and hence presents the opportunity for reevaluating algorithms for binary field arithmetic and scalar multiplication over elliptic curves. We describe how to best employ this instruction in field multiplication and the effect on performance of doubling and halving operations. Alternate strategies for implementing inversion and half-trace are examined to restore most of their competitiveness relative to the new multiplier. These improvements in field arithmetic are complemented by a study on serial and parallel approaches for Koblitz and random curves, where parallelization strategies are implemented and compared. The contributions are illustrated with experimental results improving the state-of-the-art performance of halving and doubling-based scalar multiplication on NIST curves at the 112- and 192-bit security levels and a new speed record for side-channel-resistant scalar multiplication in a random curve at the 128-bit security level. The algorithms presented in this work were implemented on Westmere and Sandy Bridge processors, the latest generation Intel microarchitectures.

Improved Division by Invariant Integers

This paper considers the problem of dividing a two-word integer by a single-word integer, together with a few extensions and applications. Due to lack of efficient division instructions in current processors, the division is performed as a multiplication using a precomputed single-word approximation of the reciprocal of the divisor, followed by a couple of adjustment steps. There are three common types of unsigned multiplication instructions: we define full word multiplication (umul), which produces the two-word product of two single-word integers; low multiplication (umullo), which produces only the least significant word of the product; and high multiplication (umulhi), which produces only the most significant word. We describe an algorithm that produces a quotient and remainder using one umul and one umullo. This is an improvement over earlier methods, since the new method uses cheaper multiplication operations. It turns out that we also get some additional savings from simpler adjustment conditions. The algorithm has been implemented in version 4.3 of the gmp library. When applied to the problem of dividing a large integer by a single word, the new algorithm gives a speedup of roughly 30 percent, benchmarked on AMD and Intel processors in the x86_64 family.

Efficient implementation of the Galois Counter Mode using a carry-less multiplier and a fast reduction algorithm

This paper describes a new method for efficient implementation of the Galois Counter Mode on general purpose processors. Our approach is based on three concepts: a) having a 64-bit carry-less multiplication instruction in the processor; b) a method for using this instruction to efficiently multiply binary polynomials of degree 127; c) a method for efficient reduction of a binary polynomial of degree 254, modulo the polynomial x 128 + x 7 + x 2 + x + 1 (which defines the finite field of the Galois Counter Mode). The two latter concepts can be used for writing an efficient and lookup-table free software implementation of the Galois Counter Mode, for processors that have a carry-less multiplication instruction. Our approach uses only a generic carry-less multiplication instruction, without any field-specific reduction logic, making the instruction applicable to multiple use cases, and therefore an appealing addition to the instruction set of a general purpose processor. This research played a significant role in the process that eventually led to adding a carry-less multiplication instruction (called PCLMULQDQ) to the Intel Architecture. PCLMULQDQ and six AES instructions are introduced in the new 2010 Intel Core processor family, based on the 32 nm Intel microarchitecture codename “Westmere”. On the new Westmere processors, the software that implements the methods described here, computes AES-GCM more than six times faster than the current, lookup table-based, state-of-the-art implementation. This new capability adds motivation to using AES-GCM for high performance secure networking.

Efficient and formally proven reduction of large integers by small moduli

On w -bit processors which are much faster at multiplying two w -bit integers than at dividing 2 w -bit integers by w -bit integers, reductions of large integers by moduli M smaller than 2 w -1 are often implemented suboptimally, leading applications to take excessive processing time. We present a modular reduction algorithm implementing division by a modulus through multiplication by a reciprocal of that modulus, a well-known method for moduli larger than 2 w -1 . We show that application of this method to smaller moduli makes it possible to express certain modular sums and differences without having to compensate for word overflows. By embedding the algorithm in a loop and applying a few transformations to the loop, we obtain an algorithm for reduction of large integers by moduli up to 2 w -1 . Implementations of this algorithm can run considerably faster than implementations of similar algorithms that allow for moduli up to 2 w . This is substantiated by measurements on processors with relatively fast multiplication instructions. It is notoriously hard to specify efficient mathematical algorithms on the level of abstract machine instructions in an error-free manner. In order to eliminate the chance of errors as much as possible, we have created formal correctness proofs of our algorithms, checked by a mechanized proof assistant.

Children’s multiplicative transformations of discrete and continuous quantities

Recent studies have documented an evolutionarily primitive, early emerging cognitive system for the mental representation of numerical quantity (the analog magnitude system). Studies with nonhuman primates, human infants, and preschoolers have shown this system to support computations of numerical ordering, addition, and subtraction involving whole number concepts prior to arithmetic training. Here we report evidence that this system supports children’s predictions about the outcomes of halving and perhaps also doubling transformations. A total of 138 kindergartners and first graders were asked to reason about the quantity resulting from the doubling or halving of an initial numerosity (of a set of dots) or an initial length (of a bar). Controls for dot size, total dot area, and dot density ensured that children were responding to the number of dots in the arrays. Prior to formal instruction in symbolic multiplication, division, or rational number, halving (and perhaps doubling) computations appear to be deployed over discrete and possibly continuous quantities. The ability to apply simple multiplicative transformations to analog magnitude representations of quantity may form a part of the toolkit that children use to construct later concepts of rational number.