Multiplierless Finite Impulse Response Filters Research Articles

Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders

This work presents two novel methods that simultaneously optimize both the design of a finite impulse response (FIR) filter and its multiplierless hardware implementation. We use integer linear programming (ILP) to minimize the number of adders used to implement a direct/transposed FIR filter adhering to a given frequency specification. The proposed algorithms work by either fixing the number of adders used to implement the products (multiplier block adders) or by bounding the adder depth (AD) used for these products. The latter can be used to design filters with minimal AD for low-power applications. In contrast to previous multiplierless FIR filter approaches, the methods introduced here ensure adder count optimality. We perform extensive numerical experiments, which demonstrate that our simultaneous filter design approach yields results that are in many cases on par or better than those in the literature.

Design of low power multiplierless FIR filter with enhanced adder efficiency using flower pollination optimization

This paper presents an improved design of minimal power multiplierless finite impulse response (FIR) by using flower pollination algorithm (FPA) and newly proposed hybrid common sub-expression elimination (CSE) algorithm. The novel extract of this paper is three fold: first, enhancement of the power performance by reducing the switching activity; second, raising adder efficiency using newly proposed hybrid CSE algorithm; and third, optimizing the frequency response characteristics of filter by controlling ripples in passband and stopband region using FPA in one step. For this purpose, the minima of an objective function is achieved, constructed as sum of integral mean squared error with allowable tolerable limits to control ripples in passband and stopband region, and the dynamic power that has computed through hamming distance (HD) between two successive filter coefficients. In addition to this, the application of recently proposed CSE reduces the amount of adders, and lowers the value of HD. The significance of proposed algorithm is measured on the basis of different performance evaluation parameter such as; stopband attenuation (As), stopband ripple (δs), passband ripple (δp), hamming distance (HD), power and amount of adders respectively.

Performance of Multiplierless FIR Filter Based on Directed Minimal Spanning Tree: A Comparative Study

This paper presents a novel low complex configuration methodology by deploying a directed minimal spanning tree (DMST) algorithm for designing digital multiplierless finite impulse response filter. This method utilizes the shift inclusive differential coefficient and common sub-expression elimination (CSE) technique to minimize the multiple constant multiplications using steepest decent approach. The attractive feature of this work lays on the detailed comparison of the cost, reconstruction error, pass-band and stop-band error by exploiting various evolutionary techniques such as cuckoo search algorithm, particle swarm optimization, artificial bee intelligence, hybrid swarm optimization and flower pollination algorithm; followed by employing hybrid SID and DMST on these techniques. For this purpose, a mean squared error-based objective function is optimized in the pass-band and stop-band region of the filter. Further, a detailed comparison of hybrid SID and DMST with other existing CSE algorithms is also illustrated. It has been observed that up to 80% reduction in number of adders can be accomplished using the proposed DMST-based approach for multiplierless filter design.

Design of multiplierless minimum-phase FIR filters using palindromic polynomials and sharpening

Minimum phase (MP) filters have all zeros inside the unit circle and have a minimum group delay and a minimum energy delay properties, especially useful in communication systems. The special class of MP filters has all zeros inside and on the unit circle. This paper presents a method for design of this class of MP FIR (Finite Impulse Response) digital filters without multipliers The method is based on palindromic polynomials and sharpening technique. The coefficients of palindromic polynomials are presented as a sum of powers of two, and consequently can be implemented by using only adders and shifts, resulting in a multiplierless design. Two classes of palindromic polynomials, having all zeros on the unit circle, are considered. Next, the sharpening technique was applied to improve the magnitude characteristic and to move zeros inside of unit circle. The choice of the design parameters is also presented. All zeros, of the designed MP filter, are inside or on the unit circle. Method is illustrated with one example.

Performance of CSE Techniques for Designing Multiplier-Less FIR Filter Using Evolutionary Algorithms

In this work, an efficient design of multiplier-less digital finite impulse response (FIR) filter is presented, where the sub-expression elimination (SE) algorithms are employed on filter coefficients, and optimization is done with evolutionary algorithms. This FIR filter is designed with novelty of optimizing the quantized coefficients inside each of the respective optimization algorithm, instead of using two separate algorithms: one for generation of optimal continuous coefficients, and second for optimizing the quantized coefficients. Comparative analysis using different SE techniques have been utilized for reducing the requirement of adders on both binary represented and canonic signed digit converted filter coefficients. The simulation results illustrate the impact of proposed algorithm along with significant reduction in number of adders.

DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications.

Design of Multiplier-less FIR filters with Simultaneously Variable Bandwidth and Fractional Delay

Low complexity and reconfigurability are the key features in emerging communication applications in order to support multi-standards and operation modes. To obtain these features, an efficient implementation of finite impulse response (FIR) filter, with Variable Bandwidth and Fractional Delay, is proposed in this paper. The reduction in the implementation complexity is achieved by converting the continuous filter coefficients to signed power of two (SPT) space. This may lead to performance degradation. Hence, in this paper, Artificial Bee Colony (ABC) optimization is deployed for finding the near optimal solution in the discrete space.

A novel analytical method for the selective multiplierless linear-phase 2D FIR filter function

In this paper, a novel analytical method for new class of selective linear-phase two-dimensional (2D) finite impulse response (FIR) filter functions generated by applying a new modified 2D Christoffel-Darboux formula for classical orthogonal Chebyshev polynomials of the first and the second kind is proposed. Fundamental research proposed in this paper is also illustrated by examples of 2D FIR filter and adequate comparison with new class of multiplierless linear-phase 2D FIR filter function given in the literature.

1D linear-phase band-pass multiplierless FIR Hilbert transformers and filters

ABSTRACTAn original analytical method, based on modified Christoffel–Darboux formula, is used in the paper in order to synthesise a linear-phase band-pass finite impulse response (FIR) filter function that can have an effect of Hilbert transformer. New structure of the band-pass FIR filter in recursive realisation, together with the corresponding difference equation, is presented providing the efficient filter solution without multipliers. Several examples of filter types for different parity of two real free integer parameters, including a particular solution of Hilbert transformer, are considered in terms of required number of adders and values of cut-off frequencies of the pass and stop bands. A comparison of the proposed band-pass filter characteristics with those of a classical filter solution is provided in the paper.

Ultra‐selective spike multiplierless linear‐phase two‐dimensional FIR filter function with full Hilbert transform effect

In this study, a novel analytical method for new class of linear-phase two-dimensional (2D) finite impulse response (FIR) filter functions with full effect of Hilbert transformer in z 1 and z 2 domains generated by applying a new modified 2D Christoffel–Darboux formula for classical orthogonal Chebyshev polynomials of the first and the second kind is proposed. Fundamental research proposed in this study is also illustrated by examples of 2D FIR filter, Hilbert transformer and adequate comparison with new class of multiplierless linear-phase 2D FIR filter function given in the literature. For all 2D FIR filter functions, comparisons are made for the same values of free real parameters, and they show the improvement of the spike sharpness.

Design optimisation of powers-of-two FIR filter using self-organising random immigrants GA

In this communication, we propose a novel design strategy of multiplier-less low-pass finite impulse response (FIR) filter with the aid of a recent evolutionary optimisation technique, known as the self-organising random immigrants genetic algorithm. Individual impulse response coefficients of the proposed filter have been encoded as sum of signed powers-of-two. During the formulation of the cost function for the optimisation algorithm, both the frequency response characteristic and the hardware cost of the discrete coefficient FIR filter have been considered. The role of crossover probability of the optimisation technique has been evaluated on the overall performance of the proposed strategy. For this purpose, the convergence characteristic of the optimisation technique has been included in the simulation results. In our analysis, two design examples of different specifications have been taken into account. In order to substantiate the efficiency of our proposed structure, a number of state-of-the-art design strategies of multiplier-less FIR filter have also been included in this article for the purpose of comparison. Critical analysis of the result unambiguously establishes the usefulness of our proposed approach for the hardware efficient design of digital filter.

Single-Stage and Cascade Design of High Order Multiplierless Linear Phase FIR Filters Using Genetic Algorithm

In this work, a novel genetic algorithm (GA) is proposed for the design of multiplierless linear phase finite impulse response (FIR) filters. The filters under consideration are of high order and wide coefficient wordlength. Both the single-stage and cascade form are considered. In a practical filter design problem, when the filter specification is stringent, requiring high filter order and wide coefficient wordlength, GAs often fail to find feasible solutions, because the discrete search space thus constructed is huge and the majority of the solution candidates therein can not meet the specification. In the proposed GA, the discrete search space is partitioned into smaller ones. Each small space is constructed surrounding a base discrete coefficient set which is obtained by a proposed greedy algorithm. The partition of the search space increases the chances for the GA to find feasible solutions, but does not sacrifice the coverage of the search. The proposed GA applies to the design of single-stage filters. When a cascade form filter is designed, for each single-stage filter meeting the filter specification generated during the course of GA, an integer polynomial factorization is applied. Design examples show that the proposed GA significantly outperforms existing algorithms dealing with the similar problems in terms of design time, and the hardware cost is saved in most cases.

Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits

This paper develops and demonstrates the design and optimization method for fixed coefficient Finite Impulse Response (FIR) filters using sub-threshold circuits to achieve the minimum energy per operation. Sub-threshold circuit current, delay, power consumption, energy per operation and temperature dependence are modeled theoretically and analyzed using Matlab. Then the filter design and optimization are presented. With a frequency characteristic of 80 dB magnitude and 9.6 kHz bandwidth, the 16-bit fixed-point coefficients of the linear phase equiripple low-pass filter are generated from Matlab. Canonical Signed Digit (CSD) arithmetic is used for multiplierless design to improve both cost and performance. The transposed structure and symmetry structure are applied to optimize the delay and cost further. Horner's rule is used to improve the precision. Tree-height reduction and subexpression sharing at Register Transfer Level (RTL) are used for further delay and cost reduction. Six versions of the filter with the same group of coefficients are designed and synthesized using Design Compiler with a 65 nm process. Synthesis results show that the area of the final version is reduced by 44% compared with the original design at a fixed frequency of 250 MHz, and at the highest frequency of each design, the area is reduce by about 23% while the performance is improved by 60%. These results show the design and optimization method developed in this paper can improve both the area and performance significantly. One adder from the synthesis netlist is simulated at the transistor-level using HSPICE to obtain characteristics of sub-threshold operations. The supply voltage varies from 1.2 to 0.08 V and temperatures from 0 to 110°C. The experiment results verify most characteristics of the sub-threshold models, but also reveal some limitations and defects of the theoretical models and previous results. The observations are discussed carefully with quantitative and qualitative analysis. For 25°C, the minimum energy point for the adder is 0.22 V. Finally, the results of the adder are used to estimate the energy per operation for the filters. For a fixed frequency of 36.4 kHz at 0.22 V, the estimated energy values vary from 4.8 to about 2.7 pJ for the six designed filters.

CSDC: a new complexity reduction technique for multiplierless implementation of digital FIR filters

We present a computation reduction technique called computation sharing differential coefficient (CSDC) method, which can be used to obtain low-complexity multiplierless implementation of finite-impulse response (FIR) filters. It is also applicable to digital signal processing tasks involving multiplications with a set of constants. The main component of our proposed CSDC method is to combine the strength of the augmented differential coefficient approach and subexpression sharing. Exploring computation reuse through algorithmic equivalence, the augmented differential coefficient approach greatly expands the design space by employing both differences and sums of filter coefficients. The expanded design space is represented by an undirected and complete graph. The problem of minimizing the adder cost (the number of additions/subtractions) for a given filter is transformed into a problem of searching for an appropriate subexpression set that leads to a minimal adder cost. A heuristic search algorithm based on genetic algorithm is developed to search for low-complexity solutions over the expanded design space in conjunction with exploring subexpression sharing. It is shown that up to 70.1% reduction in the adder cost can be obtained over the conventional multiplierless implementation. Comparison with several existing techniques based on the available data shows that our method yields comparable results for multiplierless FIR filter implementation.

Multiplierless FIR filter design algorithms

This letter concerns the design of multiplierless implementations of finite impulse response (FIR) filters to achieve minimum adder cost. Existing approaches include dependence-graph multiplier-block methods and Common Subexpression Elimination (CSE) techniques applied either to the Canonic Signed Digit (CSD) representation of the coefficients or to other Signed Digit (SD) representations. We introduce a new CSE algorithm, which searches a bounded number of Minimal Signed Digit (MSD) representations. The performance of existing algorithms and the new algorithm is compared. It is shown that the relative performance of different algorithms depends on filter length and wordlength and that the new algorithm gives significant improvements in some cases.

An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients

An improved algorithm is presented for the discrete optimization of finite-impulse-response (FIR) digital filter coefficients which are represented by a canonic signed-digit (CSD) code, i.e., numbers representable as sums or differences of powers-of-two. The proposed search algorithm allocates an extra nonzero digit in the CSD code to the larger coefficients to compensate for the very nonuniform nature of the CSD coefficient distribution. This results in a small increase in the filter complexity; however, the improvement in the frequency response is substantial. The coefficient optimization is performed in two stages. The first stage searches for an optimum scale factor and the second stage consists of a local bivariate search in the neighborhood of the scaled and rounded coefficients. >