Multiplier Circuitry Research Articles

DC-Transformer Modelling, Analysis and Comparison of the Experimental Investigation of a Non-Inverting and Non-Isolated Nx Multilevel Boost Converter (Nx MBC) for Low to High DC Voltage Applications

This paper mainly focuses on the analysis, DC-transformer modeling, comparison, and experimental investigation of a non-inverting and non-isolated Nx multilevel boost converter (Nx MBC) for low to high DC applications. Recently, numerous isolated and non-isolated DC-DC converter configurations have been addressed for low to high DC voltage conversion purposes, which is vital for several applications (e.g., renewable energy, medical equipment, hybrid vehicles, fuel cells, DC-links, multilevel inverters, and drive applications), by utilizing and modifying the structure of reactive elements (switched capacitors and switched inductor circuitry). Among all the switched reactive structures, voltage multiplier circuitry provides a feasible solution for low to high DC voltage conversion due to its flexible and modular structure, voltage clamping capability, reduced rating of components, and ease of modification. Non-inverting and non-isolated Nx MBC combine the features and structures of conventional boost converters and voltage multiplier circuitry. DC-transformer modeling of Nx MBC is discussed for the continuous current mode (CCM) and discontinuous current mode (DCM), which helps to analyze the characteristics of the converter in a more practical way and helps to study the effect of semiconductor components, internal resistances, and load on the voltage conversion ratio of the converter. The mode of operation of Nx MBC in the CCM and DCM is also discussed with the boundary condition. The derived analysis is verified by simulations and experimental investigations, and the obtained results of 3x MBC always show good agreement with each other and the theoretical analysis.

Network design of ultra low voltage multiplier

The conditions of transition of the operating conditions of the traditional differential stage constructed MOSFET to conditions ultra low voltage mode as multiplier signal by the weighting coefficients of +1 and -1. The features of this multiplier circuitry signal constituting the basis of a programmable correlation filter. The main sources of multiplication errors are discussed and analytical assessment of their value is made. The conditions for conversion of the output signal, the product of multiplication. Practical schemes for output current-voltage converting are developed. Reference 5, figures 5.

Limits of predictive current-ripple suppression in switching power-supply ICs

Large inductance requirements (for accuracy) in switching power supplies for portable applications impede system-on-chip (SoC) integration and therefore form-factor reduction because on-chip inductances are invariably low and off-chip inductors intolerably obtrusive. Cancelling the current ripple of innately small on-chip inductors, however, keeps the effective output current ripple and its resulting output voltage variation (i.e. accuracy) within acceptable window limits (e.g. 50–200 mA and 20–50 mV), effectively multiplying the on-chip inductance and circumventing the need for bulky off-chip inductors. To this end, while gyrators and other voltage-mode inductor multiplier circuitry simulate relatively high inductances, they cannot supply the 250–750 mW loads typically attached to battery-powered switching regulators, which the predictive current-mode multipliers discussed in this paper can. The basic objective is to cancel the ac inductor current ripple with an inverting ac replica and allow the on-chip inductor to source the full dc load. Ac mismatches in the form of amplitude, delay and non-linearity, however, limit the extent to which the original ac ripple is cancelled, constraining the inductor multiplication factor to finite values. The foregoing paper describes, illustrates and derives the effects of these mismatches on the multiplication factor and shows how realistic non-idealities (e.g. up to 10% gain error and less than 10 ns of delay) can yield inductance multiplication factors of 125 H/H at 100 kHz and 11.5 H/H at 10 MHz in a practical switching dc–dc power-supply integrated circuit (IC).

A novel 3-D integrated HFET/RTD frequency multiplier

A merged heterostructure field-effect transistor/resonant tunneling diode (HFET/RTD) combination is proposed to act as a (sub)millimeter wave source via highly efficient frequency multiplication and its functionality is demonstrated at intermediate frequency. On a semi-insulating InP-substrate a HFET followed by a double barrier RTD-layer sequence is grown in a single molecular beam epitaxy (MBE)-run. A novel monolithic frequency multiplier circuitry is developed where the RTD is used as load in contrast to other concepts where the RTD is inserted in the input of a three-terminal device. The resulting output voltage is rectangular type and rich in higher odd harmonics. This approach avoids classical disadvantages of the RTD because biasing in the negative-differential-regime is not required and bistability of the I-V-characteristic is used rather than the negative differential resistance. The small signal parameters of the single devices realized with optical lithography, wet etching, and self-aligned process technology are used as input data for a microwave design software (MDS) and the frequency multiplication is modeled up to submillimeter wave frequencies.

Isotope ratio and trace element imaging of pyrite grains in gold ores

Secondary ion mass spectrometry techniques for imaging measurements of 34S/ 32S isotope ratios and quantitative trace element concentrations in pyrite mineral grains have been demonstrated. Test samples show that the 34S/ 32S isotope ratios are constant within Poisson error, independent of image position. Variable 34S/ 32S isotope ratios have been found within a a single pyrite grain in a sample of gold ore from the Carlin mine in the Carlin District of Nevada. The locations of trace gold concentrations in this ore sample correlate with relative 34S enrichment. Imaging has the inherent problem of spreading already limited minor isotope signals among many pixels. This problem can be overcome with improved analysis methodology including new electron multiplier circuitry to accommodate more intense secondary ion signals, stable data collection over relatively long time periods, and improved software. High mass resolution imaging and careful neutralization of ion beam induced sample charging are also required.

Simultaneous measurement of the in-phase and quadrature components of the signal in A.C. polarography using multiplier circuitry

Simultaneous measurement of the in-phase and quadrature components of the signal in A.C. polarography using multiplier circuitry

Simultaneous measurement of the in-phase and quadrature components of the signal in a.c. polarography using multiplier circuitry

The use of multiplier circuitry is shown to provide a simple way of simultaneously measuring the in-phase and quadrature (phase-angle) components of the signal in alternating current polarography. When used with previously developed circuitry an extremely versatile instrumental approach is available for detecting the second harmonic and intermodular (frequency difference) components in addition to the in-phase and quadrature components of the fundamental harmanic.

A low-power, bipolar, two's complement serial pipeline multiplier chip

A 4-bit, general-purpose, two's complement serial pipeline multiplier chip has been designed and fabricated in the bipolar GIMIC-O process. The chip can provide the following functions in 24-pin dual-in-line packages: (1) two's complement/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (2) sign magnitude/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (3) 5-bit dynamically programmable adder/subtractor, (4) 2/SUP -K/ scaler; (5) overflow corrector. Packages can be cascaded to provide functions of length greater than 4 bits. Nonsaturating circuit techniques, emitter function logic combined with current-steering trees, are effectively utilized to make high-performance, low-power circuits using a simple bipolar technology. The multiplier circuitry is compatible at inputs and outputs with standard emitter coupled logic and uses a standard -5.2/spl plusmn/10 percent power supply. Fully programmable multiplication at clock rates greater than 20 MHz is achieved with a power consumption of 37.5 mW/bit.