Multiplication In Elliptic Curve Cryptography Research Articles

Lookup Table-Based Design of Scalar Multiplication for Elliptic Curve Cryptography

This paper is aimed at using a lookup table method to improve the scalar multiplication performance of elliptic curve cryptography. The lookup table must be divided into two polynomials and requires two iterations of point doubling operation, for which negation operations are needed. It is well known that an inversion operation requires a lot of multiplication time. The advantage of this paper is that we are able to reduce one inverse element calculation for this problem and also improve the basic operations of finite fields through segmentation methods. If the normal basis method is used in the design of the inverse element operation, it must be converted to the normal basis through the standard basis. However, the conversion process requires a lot of matrix operations. Though the anti-element operation has good speed performance, it also increases the computational complexity. Using number theory and grouping methods will greatly improve the performance of inverse element operations. With application of the two-time point doubling operation in the hardware implementation, the developed approach reduces the computing time by 48% as compared with the conventional approach. The computational time of the scalar multiplication using the presented method is further improved by 67% over the traditional algorithm with only an area increase of 12%. Finally, the proposed lookup table-based technique can be utilized for software and hardware implementation, as the developed arithmetic operations are simple and are consistent in their execution.

Enhanced Scalar Multiplication Algorithm over Prime Field Using Elliptic Net

Scalar multiplication in elliptic curve cryptography is the most expensive and time-consuming operation. The elliptic curve cryptography attracted interest due to the development of modern technology since it could offer the equivalent high level of security with a reduced length of key. Therefore, improving elliptic curve scalar multiplication performance has always been the primary goal of cryptography. In this paper, a novel scalar multiplication algorithm based on the modified double and double add via elliptic net with Karatsuba method was proposed in order to enhance the efficiency of scalar multiplication. In the experimental results, the elliptic net equivalence sequence was applied to the Twisted Edwards curve together with safe curves of numsp384t1 and numsp512t1. At the point operational level, the proposed method reduced the cost of multiplication by 46.15% and 42.30% for double and double add, respectively, when compared to elliptic net using eight blocks method. The proposed double lowered the multiplication cost by 12.5% and the squaring cost by 20% when compared to elliptic net using ten temporary variables method. Following this, proposed double add cost reductions of 6.25% and 20% were obtained to multiplication and squaring. At the field operational level, in comparison to the binary method, the eight-block elliptic net method, and the elliptic net method with ten temporary variables for the 384 bits scenario, the developed scalar multiplication algorithm obtained cost reductions of 57.6%, 31.3%, and 13.2%, respectively. On 512 bits with similar comparison, the designed algorithm exhibited better performance by averages 59.2%, 31.0% and 13.2%. The results signified that the designed algorithm over prime field performed better at the point and field operational levels with larger scalar bit size.

Efficient scalar multiplication of ECC using SMBR and fast septuple formula for IoT

In order to solve the problem between low power of Internet of Things devices and the high cost of cryptography, lightweight cryptography is required. The improvement of the scalar multiplication can effectively reduce the complexity of elliptic curve cryptography (ECC). In this paper, we propose a fast formula for point septupling on elliptic curves over binary fields using division polynomial and multiplexing of intermediate values to accelerate the computation by more than 14%. We also propose a scalar multiplication algorithm based on the step multi-base representation using point halving and the septuple formula we proposed, which significantly reduces the computational cost. The experimental results show that our method is more efficient over binary fields and contributes to reducing the complexity of ECC.

Innovative Dual-Binary-Field Architecture for Point Multiplication of Elliptic Curve Cryptography

High-performance Elliptic Curve Cryptography (ECC) implementation in encryption authentication severs has become a challenge due to the explosive growth of e-commerce’s demand for speed and security. Point multiplication (PM) is the most common and complex operation in ECC which directly determines the performance of the whole system. This article proposes a 6CC-6CC (clock cycle) dual-field PM architecture and a 6CC-4CC dual-field PM architecture based on maximizing utilization of Karatsuba multipliers and re-ordering schedule strategy in PM. The Montgomery Ladder algorithm used in PM is modified to a 4CC algorithm for better resource utilization and parallel computation. To solve the frequency drop problem while working on large finite field, the PM architectures for high and low field are carefully studied to have universal critical path length and balanced performance. Both of the architectures are implemented over GF(2571) and GF(2283) on Xilinx Virtex-5 and Virtex-7 FPGAs (Field-Programmable Gate Array) for comparison. The 6CC-6CC architecture is shown to have the best performance on GF(2571), which achieves one PM operation in $17.44~\mu s$ using 81549 LUTs (Look-Up-Table) with the frequency of 197.2 MHz on Virtex-5, and $12.55~\mu s$ using 80970 LUTs with the frequency of 274.1 MHz on Virtex-7. The 6CC-4CC architecture performs better on GF(2283) with the shortest computation time. It takes only $3.21~\mu s$ to finish one PM operation on Virtex-5 and $2.22~\mu s$ on Virtex-7, which are faster than all the previous designs. The implementation results prove that the proposed architectures have state-of-the-art performance as well as higher versatility for ECC designs.

Efficient implementation of modular multiplication over 192-bit NIST prime for 8-bit AVR-based sensor node

Modular multiplication is one of the most time-consuming operations that account for almost 80% of computational overhead in a scalar multiplication in elliptic curve cryptography. In this paper, we present a new speed record for modular multiplication over 192-bit NIST prime P-192 on 8-bit AVR ATmega microcontrollers. We propose a new integer representation named Range Shifted Representation (RSR) which enables an efficient merging of the reduction operation into the subtractive Karatsuba multiplication. This merging results in a dramatic optimization in the intermediate accumulation of modular multiplication by reducing a significant amount of unnecessary memory access as well as the number of addition operations. Our merged modular multiplication on RSR is designed to have two duplicated groups of 96-bit intermediate values during accumulation. Hence, only one accumulation of the group is required and the result can be used twice. Consequently, we significantly reduce the number of load/store instructions which are known to be one of the most time-consuming operations for modular multiplication on constrained devices. Our implementation requires only 2888 cycles for the modular multiplication of 192-bit integers and outperforms the previous best result for modular multiplication over P-192 by a factor of 17%. In addition, our modular multiplication is even faster than the Karatsuba multiplication (without reduction) which achieved a speed record for multiplication on AVR processor.

A Hybrid Addition Chaining Based Light Weight Security Mechanism for Enhancing Quality of Service in IoT

IoT in Wireless Sensor Networkis a network of physical objects connected to internet such as RFID and sensors. As these types of objects have limited computation power and memory, execution of public key cryptography would be a daunting task. So a light weight encryption with Elliptic Curve Cryptography (ECC) is proposed in this work. A major issue in ECC is its computational cost as it is complicated to compute the scalar multiplication. To address this issue, a novel method called graph based addition chaining (GBAC) is proposed. This graph technique produces all possible optimum addition chains for the given integer n by utilizing edge weight of all possible numbers created from each number of addition chain. This addition chain technique can be used in modular exponentiation which is an essential step in the implementation of public cryptographic algorithms like ElGamal, RSA, etc., so that the time for encryption and decryption for these algorithms can be reduced drastically. The proposed GBAC technique has used addition chaining technique instead of scalar multiplication in ECC which greatly reduces the computation time as well as computation cost. It also reduces the complexity in ECC. Numerous experiments has been made and proved that our work decreases the decryption time by at least 10% than RSA algorithm, reduces computation cost and improves the performance of parameters like CPU time, Memory requirement and key preparation time and better than RSA in decryption.

RETRACTED ARTICLE: Performance improvement of elliptic curve cryptography system using low power, high speed 16 × 16 Vedic multiplier based on reversible logic

Multipliers act as processors and take on the notable work of many computing frameworks. The speed of the processor is profoundly affected by the speed of their multipliers. In order to improve the system speed, faster and more efficient multipliers should be used. A Vedic multiplier is one of the best solution that can be used to perform multiplications at a faster rate by eliminating the steps that are not needed in usual multiplication process. Power consumption is another critical issue in embedded systems that cannot be ignored. Reversible logic has become notable in the recent years because of its potential to reduce power utilization, which is a major concern in digital design. In this work, a high-speed 16 × 16 Vedic multiplier was designed using Urdhva Tiryagbhyam (UT) sutra, which is derived from Vedic mathematics. This is a simple structure as well as an unbeatable combination for creating any complex multiplication operations for services where speed is of prime importance. This work also proposes a new method based on Elliptic Curve Cryptography (ECC) system for encryption and decryption using Vedic multiplication. By using Vedic Multiplication in ECC the processing time is perfectly reduced. The proposed Elliptic curve cryptography method is much faster than other elliptic curve cryptographic algorithms. Compared to other cryptographic techniques, the key size required to provide equivalent security is small in ECC.

Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography

In this paper, an area-time efficient hardware implementation of modular multiplication over five National Institute of Standard and Technology (NIST)-recommended prime fields is proposed for lightweight elliptic curve cryptography (ECC). A modified radix-2 interleaved algorithm is proposed to reduce the time complexity of conventional interleaved modular multiplication. The proposed multiplication algorithm is designed in hardware and separately implemented on Xilinx Virtex-7, Virtex-6, Virtex-5, and Virtex-4 field-programmable gate array (FPGA) platforms. On the Virtex-7 FPGA, the proposed design occupies only 1151, 1409, 1491, 2355, and 2496 look up tables (LUTs) and performs single modular multiplication in 0.93 μs, 1.18 μs, 1.45 μs, 2.80 μs, and 4.69 μs with maximum clock frequencies of 207.1 MHz, 190.7 MHz, 177.3 MHz, 137.6 MHz, and 111.2 MHz over five NIST prime fields of size 192, 224, 256, 384, and 521 bits, respectively. The hardware implementations on the Virtex-6, Virtex-5, and Virtex-4 FPGAs also show that the proposed design is highly efficient in terms of hardware resource utilization and area-delay product compared with other designs for modular multiplication.

Throughput/area optimised pipelined architecture for elliptic curve crypto processor

A pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first; by pipelining the arithmetic unit to reduce the critical path delay. Second, by reducing the number of clock cycles (latency), which is achieved through careful scheduling of computations involved in point addition and point doubling. These two factors thus, help in reducing the time for one point multiplication computation. On the other hand, the small area overhead for this design gives a higher throughput/area ratio. Consequently, the proposed architecture is synthesised on different FPGAs to compare with the state-of-the-art. The synthesis results over GF(2 m ) show that the proposed design can work up to a frequency of 369, 357 and 337 MHz when implemented for m = 163, 233 and 283 bit key lengths, respectively, on Virtex-7 FPGA. The corresponding throughput/slice figures are 42.22, 12.37 and 9.45, which outperform existing implementations.

Speed-Oriented Architecture for Binary Field Point Multiplication on Elliptic Curves

This paper introduces a novel speed-oriented architecture of point multiplication in elliptic curve cryptography. A balanced full-precision multiplier is proposed to shorten latency, and a new modular inversion architecture is integrated to reduce the total number of clock cycles in point multiplication. A modified Montgomery Ladder algorithm that takes three clock cycles to calculate one input bit is proposed to best utilize hardware resources. A mixed-pipeline technique is used to balance the delay of different paths and increase frequency. The proposed architecture is implemented on GF(2163) and GF(2571), based on Xilinx Virtex-5 and Virtex-7 FPGA. For GF(2163), the design reaches 211 MHz, with 29309 LUTs, and 547 clock cycles or $2.6~\mu \text{s}$ latency on Virtex-5; 320.5 MHz, with 28911 LUTs and $1.7~\mu \text{s}$ latency on Virtex-7. For GF(2571), the design reaches 186 MHz, with 286400 LUTs, and 1813 clock cycles or $9.6~\mu \text{s}$ latency on Virtex-5; 267 MHz, 290001 LUTs and $6.79~\mu \text{s}$ latency on Virtex-7. The proposed design achieves the lowest latency among all existing works, and its performance is also among the top. Furthermore, it is demonstrated that the proposed architecture maintains a high speed for larger binary fields, making it more suitable to be implemented in large-bit-length platforms with a higher security level. Since the multiplier and its segments work in different bit-length and refer to different fields, the proposed architecture can also be upgraded to a reconfigurable design to support multiple-field point multiplication in the future.

Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic

In this paper, a high-speed power-efficient VLSI implementation of a finite field multiplier in GF( $2^{m}$ ) is presented. The proposed design has a serial-in parallel-out architecture and performs the multiplication operation using a reordered normal basis. The basic idea is to implement the main building block of the multiplier in domino logic to reduce the critical path delay. Reduction in dynamic power consumption is achieved by limiting the contention current between the keeper transistor and the pull-down network at the beginning of the evaluation phase by employing a new keeper control circuit. The semicustom layout of the multiplier was realized in 65-nm CMOS technology. The post place-and-route simulations showed that the multiplier can perform multiplication correctly up to a clock rate of 3.85 GHz and consumes marginally less power than the static CMOS counterpart (also implemented with custom placement and route). The size of the multiplier is currently recommended by the National Institute of Standards and Technology for binary field multiplication in elliptic curve cryptography. The proposed design methodology can also be used in the implementation of similar finite field multipliers possessing regular architectures.

Gaussian normal basis multiplier over GF(2m) using hybrid subquadratic‐and‐quadratic TMVP approach for elliptic curve cryptography

In recent years, subquadratric‐and‐quadratric Toeplitz matrix–vector product (TMVP) computations are widely used for the implementation of binary field multiplication in elliptic curve cryptography. Pure subquadratric TMVP structure involves significantly less space complexity and long computational delay, while quadratric TMVP structure involves larger space complexity and less computation delay. To optimise the tradeoff between time and space complexities, this study presents a novel hybrid multiplier for Gaussian normal basis (GNB) in GF(2m) which combines subquadratic and quadratic structures. From the theoretical analysis, it is shown that the proposed hybrid multiplier can save ∼18% space complexity and 12% time complexity than the existing GNB multiplier with pure TMVP decomposition.

Secure GCM implementation on AVR

In Internet of Things (IoT), sensor devices should deliver the collected sensor data to the server after the data is encrypted. The encrypted data cannot be eavesdropped by adversaries but the side channel information including clock cycles and power consumption patterns during encryption operations can leak the secret information. For this reason, cryptography engineering should prevent potential threats by designing the cryptography functions in secure manner. In this paper, we explore the feasible side channel attacks on cryptography operations, particularly polynomial multiplication for Galois/Counter Mode of operation (GCM). We perform the horizontal Correlation Power Analysis (CPA) on the most well-known Lopez et al.’s polynomial multiplication and successfully extract the secret values from power consumption patterns. In order to prevent proposed attack model, we suggest a masked polynomial multiplication, ensuring a regular and constant-time solution without potential vulnerabilities including Look-up Table (LUT) access and branch statements. With proposed polynomial multiplication, we suggest the secure and efficient implementation of GCM on the low-end embedded processor. Finally, we further explore the long polynomial multiplication for Elliptic Curve Cryptography (ECC) operations. We exploit the combination of Karatsuba algorithm and proposed masked polynomial multiplication, which achieved the practically fast polynomial multiplication on embedded processors.

A Synthesis of Multi-Precision Multiplication and Squaring Techniques for 8-Bit Sensor Nodes: State-of-the-Art Research and Future Challenges

Multi-precision multiplication and squaring are the performance-critical operations for the implementation of public-key cryptography, such as exponentiation in RSA, and scalar multiplication in elliptic curve cryptography (ECC). In this paper, we provide a survey on the multi-precision multiplication and squaring techniques, and make special focus on the comparison of their performance and memory footprint on sensor nodes using 8-bit processors. Different from the previous work, our advantages are in at least three aspects. Firstly, this survey includes the existing techniques for multiprecision multiplication and squaring on sensor nodes over prime fields. Secondly, we analyze and evaluate each method in a systematic and objective way. Thirdly, this survey also provides suggestions for selecting appropriate multiplication and squaring techniques for concrete implementation of public-key cryptography. At the end of this survey, we propose the research challenges on efficient implementation of the multiplication and the squaring operations based on our observation.

High performance MAC unit for DSP and cryptographic applications

Multiplication and addition are the basic arithmetic operation used in Digital Signal Processing (DSP) for coefficient multiplication, scalar point multiplication in Elliptic Curve Cryptography (ECC) and in other fields. Multiplications are basically a shift and add operation. However, there are many different variations on how to do it. Some are more suitable to implement on FPGA than others. However time complexities and hardware complexities are the major issues in designing a multiplier unit. There are different multiplication algorithms in current technology. Hardware complexities in some design are more than time complexities whereas in some other design time complexities are more. However there must be a tradeoff between these two types of methodology. This paper will discuss a brief idea how a tradeoff can be achieved. Experimental results that have discussed here and the architecture based on the proposed algorithm shows it's novelty. Applications of the proposed algorithm on DSP and ECC have been dealt here clearly.

New Algorithm to Convert any Integer in TBNS

Algebraic complexity of different Algorithms in Signal Processing and Cryptography leads to a major problem and Researchers are trying to develop new Algorithms to solve these problems. To enhance the speed of the existing Algorithms, different number system have been found for point multiplication in elliptic curve cryptography and coefficient multiplication in digital signal processing manly for digital filter design. Among the different number system, DBNS, DBC, HBTJSF, w-NAF are efficient. Recently, to increase the speed again, TBNS, SDTBNS have been developed. There are different method to convert any integer or fraction into TBNS and hence SDTBNS. Here a new algorithm will be discussed which increase the conversion efficiency.

Efficient Implementation of Scalar Multiplication for Elliptic Curve Cryptography using Ancient Indian Vedic Mathematics over GF(p)

Elliptic Curve Cryptography (ECC) is one of the safest standard algorithms, based on public-key, for providing the security in communication and networks. One of the most time consuming processes in ECC algorithm for encryption/decryption is the scalar multiplication, i.e., KP, where P is the text which is on the elliptic curve. This paper examines that computation can be speeded up by using Ancient Indian Vedic Mathematics. Coding is done using Verilog-HDL and downloaded on target device as Virtex 5. Our proposed work is six times faster than the previous work when applied in point doubling using Spartan3 as target device.

A Fast Hardware Architecture for Integer to \tauNAF Conversion for Koblitz Curves

Scalar multiplication in elliptic curve cryptography is the most computational intensive operation. Efficiency of this operation can be significantly improved in hardware implementations by using Frobenius endomorphisms which require integer to <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">τ</sub> -adic nonadjacent form conversion. Because conversion is one of the limiting factors in some of Koblitz curve-based cryptosystems, it has become an interesting problem. In this paper, we propose two algorithms and a novel hardware architecture to double the speed of integer to <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">τ</sub> -adic nonadjacent form conversion.

Shorter addition chain for smooth integers using decomposition method

An efficient computation of scalar multiplication in elliptic curve cryptography can be achieved by reducing the original problem into a chain of additions and doublings. Finding the shortest addition chain is an NP-problem. To produce the nearest possible shortest chain, various methods were introduced and most of them depends on the representation of a positive integer n into a binary form. Our method works out the given n by twice decomposition, first into its prime powers and second, for each prime into a series of 2’s from which a set of rules based on addition and doubling is defined. Since prime factorization is computationally a hard problem, this method is only suitable for smooth integers. As an alternative, the need to decompose n can be avoided by choosing n of the form . This shall not compromise the security of ECC since its does not depend on prime factorization problem. The result shows a significant improvement over existing methods especially when n grows very large.

A SINGLE FORMULA AND ITS IMPLEMENTATION IN FPGA FOR ELLIPTIC CURVE POINT ADDITION USING AFFINE REPRESENTATION

A formula for point addition in elliptic curves using affine representation and its implementation in FPGA is presented. The use of this new formula in hardware implementations of scalar multiplications for elliptic curve cryptography has the main advantages of: (i) reducing area for the implementations of elliptic curve point addition, and (ii) increasing the resistance to side channel attacks of the hardware implementation itself. Hardware implementation of scalar multiplication for elliptic curve cryptography using this new formulation requires low area resources while keeping high performance compared to implementations using projective coordinates, which are usually considered faster than the affine coordinates.