Multiple Voltage-frequency Islands Research Articles

Multiobjective Approach to Schedule DAG Tasks on Voltage Frequency Islands

Scheduling a Directed Acyclic Graph (DAG) on voltage frequency islands involves dividing the available processing units into multiple islands with varying voltage and frequency levels, and then mapping the tasks of the DAG to the islands while minimizing the makespan and overall energy consumption. In this research work, a novel DAG task scheduling model is introduced with the assistance acquired from the deep learning paradigm. The proposed model includes four major phases: (a) DAG modelling, (b) Voltage frequency island partitioning, (c) core temperature prediction and (d) scheduling optimization. Initially, the Directed Acyclic Graph (DAG) model is designed. The nodes of DAG represent tasks and the edges represent dependencies between tasks. Then, in the Voltage frequency island partitioning, the available processing units into multiple voltage frequency islands. This can be done based on the power consumption of each unit, and the task requirements. Subsequently, the Recurrent Neural Network (RERNN) is trained to predict the core temperature of each voltage frequency island based on the multi-objectives like execution time, makespan, overall energy consumption. Then, the scheduling of the DAG on the voltage frequency islands is optimized using the Self-Improved Pelican Optimization Algorithm (SI-POA). The proposed SI-POA model is an extended version of the standard POA model. The SI-POA model is inspired by the behavior by the natural behavior of pelicans during hunting. In the scheduling optimization phase, the SI-POA algorithm to optimize the scheduling of the DAG on the voltage frequency islands while taking into account the predicted core temperature of each island based on the Recalling-enhanced recurrent neural network (RERNN) model. The goal is to minimize the makespan and overall energy consumption of the DAG while keeping the core temperature of each island within safe limits.

Optimality of dynamic voltage/frequency scaling in many-core systems with voltage-frequency islands

In today’s multicore systems, depending on an application’s computational demand, cores are either operated individually at different Voltage/Frequency (V/F) levels or grouped into multiple Voltage-Frequency Islands (VFIs) to reduce system energy consumption. This paper formulates a task scheduling and VFI partitioning problem whose optimization goal is to minimize the task set (application) execution time (makespan) for a given energy budget. First, the constrained optimization problem is formulated with integer Linear Programming (ILP) to obtain per-core, per-task dynamic V/F levels in a fine-grain VFI-based system with single-core islands. Next, static task scheduling on coarse-grain VFI-based systems, where an island can contain several cores operated at the same V/F level, is formulated with Mixed integer Linear Programming (MILP), considering the energy budget and task set’s precedence constraints. As an extension of this work and to address varying computational workload of the applications at runtime, this paper proposes a DVFS-enabled VFI system, which forms the VFIs based on the cores’ workload similarities and dynamically adjusts the VFIs’ V/F levels over the applications’ execution phases. The experimental results show that under different energy budget constraints, fine-grain, dynamic task allocations provide on average 1.35x speedup over static coarse-grain scheduling and partitioning methods. Also, the results show that while our dynamically tuned VFI system’s performance is comparable to the fine-grain V/F assignment technique, compared to the static task scheduling/VFI partitioning method, it achieves on average 1.5x speedup across the applications considered in this study.

Energy Efficiency for Clustered Heterogeneous Multicores

Heterogeneous multicore systems clustered in multiple Voltage Frequency Islands (VFIs) are the next-generation solution for power and energy efficient computing systems. Due to the heterogeneity, the power consumption and execution time of a task changes not only with Dynamic Voltage and Frequency Scaling (DVFS), but also according to the task-to-island assignment, presenting major challenges for power management and energy minimization techniques. This paper focuses on energy minimization of periodic real-time tasks (or performance-constrained tasks) on such systems, in which the cores in an island are homogeneous and share the same voltage and frequency, but different islands have different types and numbers of cores and can be executed at other voltages and frequencies. We present an efficient algorithm to minimize the total energy consumption while satisfying the timing constraints of all tasks. Our technique consists of the coordinated selection of the voltage and frequency levels for each island, together with a task partitioning strategy that considers the energy consumption of the task executing on different islands and at different frequencies, as well as the impact of the frequency and the underlying core architecture to the resulting execution time. Every task is then mapped to the most energy efficient island for the selected voltage and frequency levels, and to a core inside the island such that the workloads of the cores in a VFI are balanced. We experimentally evaluate our technique and compare it to state-of-the-art solutions, resulting in average in 25 percent less energy consumption (and up to 87 percent for some cases), while guaranteeing that all tasks meet their deadlines.

Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty

Multiple voltage frequency island (VFI)-based designs can reduce the energy dissipation in multicore platforms by taking advantage of the varying nature of the application workloads. Indeed, the voltage/frequency (V/F) levels of the VFIs can be dynamically tailored by considering the workload-driven variations in the application. Traditionally, mesh-based networks-on-chip (NoCs) have been used in VFI-based systems; however, they have large latency and energy overheads due to the inherently long multihop paths. Consequently, in this paper, we explore the emerging paradigm of wireless NoC (WiNoC) and demonstrate that by incorporating WiNoC, VFI, and dynamic V/F tuning in a synergistic manner, we can design energy-efficient multicore platforms without introducing noticeable performance penalty. Our experimental results show that for the benchmarks considered, the proposed approach can achieve between 5.7% and 46.6% energy-delay product (EDP) savings over the state-of-the-art system and 26.8% and 60.5% EDP savings over a standard baseline non-VFI mesh-based system. This opens up a new of class of codesign approaches that can make WiNoCs the communication technology of choice for future multicore platforms.

Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs

Multiple Voltage Frequency Island (VFI)-based designs can reduce the energy dissipation in multicore chips. Indeed, by tailoring the voltages and frequencies of each VFI domain, we can achieve significant energy savings subject to specific performance constraints. The achievable performance of VFI-based multicore platforms depends on the overall communication backbone, which relies predominantly on Networks-on-Chip (NoCs). Traditionally mesh-based NoCs have been used in VFI-based systems. However, the mesh-based NoCs have large latency and energy overheads due to their inherently long multihop paths. Emerging paradigms such as the millimeter (mm)-wave small-world wireless Networks-on-Chip (mSWNoCs) have lately been observed to help reduce the impact of the communication backbone on the performance of the multicore chips. In this work, we demonstrate that not only do mSWNoC-enabled VFI designs mitigate some of the full-system performance degradation inherent in VFI-partitioned multicore designs, but they also help in eliminating it entirely for certain applications. We also demonstrate that the VFI-partitioned designs used in conjunction with a novel NoC architecture like mSWNoC can achieve significant energy savings while minimizing the impact on the performance for each application under consideration.

Networks‐on‐Chip: Architectures, Design Methodologies, and Case Studies

As the density of VLSI design increases, more processors or cores can be placed on a single chip. Therefore, the design of a Multi-Processor System-on-Chip (MP-SoC) architecture, which demands high throughput, low latency, and reliable global communication services, cannot be done by just using current bus-based on-chip communication infrastructures. Networks-on-Chip (NoC) has been proposed in recent years as a promising solution of on-chip interconnection network to provide better scalability, performance, and modularity for current and future MP-SoC architectures. The paper entitled “Networks on chips: structure and design methodologies” introduces several NoC architectures and discusses the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Then, a novel Bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is presented, which can break the performance bottleneck caused by bandwidth restriction in conventional NoCs. Since buffers in on-chip networks constitute a significant proportion of the power consumption and the area of interconnects, reducing the buffer size is an important problem. The paper entitled “A buffer sizing algorithm for network on chips with multiple voltage-frequency islands” describes a two-phase algorithm to size the switch buffers in NoC in considering the support of multiple-frequency islands. The paper entitled “Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks” depicts the design of an energy-efficient and reliable channel for on-chip interconnection networks (OCINs) using a self-calibrated voltage scaling technique with self-corrected green (SCG) coding scheme. Among the NoC components, links that connect the NoC routers are the most power-hungry components. The paper entitled “Intelligent on/off dynamic linkmanagement for onchip networks” presents an intelligent dynamic power management policy for NoCs with improved predictive abilities based on supervised online learning of the system status, where links are turned off and on via the use of a small and scalable neural network. Monitoring and diagnostic systems are required in modern NoC implementations to assure high performance and reliability. In the paper entitled “Status data and communication aspects in dynamically clustered network-onchip monitoring,” the design of a dynamically clustered NoC monitoring structure for traffic and fault monitoring is illustrated. Since biological organisms have better adaptability than computer systems in dealing with environmental changes or noise. A case study on the design of an evolvable neuromolecular hardware motivated from some biological evidence, which integrates interand intra-neuronal information processing, is depicted in the paper entitled “A hardware design of neuromolecular network with enhanced resolvability: a bio-inspired approach.”

Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip

The design of many core systems-on-chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption and clock distribution problems. To deal with these issues, we consider network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) and propose a design methodology for runtime energy management. The proposed approach minimizes the energy consumption subject to performance constraints. Then, we present efficient techniques for on-the-fly workload monitoring and management to ensure that the system can cope with variability in the workload and various technology-related parameters. Simulation results demonstrate the effectiveness of our approach in reducing the overall system energy consumption for a real video application. Finally, the results and functional correctness are validated using an field-programmable gate-array (FPGA) prototype for an NoC with multiple VFIs.

System-level throughput analysis for process variation aware multiple voltage-frequency island designs

The increasing variability in manufacturing process parameters is expected to lead to significant performance degradation in deep submicron technologies. Multiple Voltage-Frequency Island (VFI) design styles with fine-grained, process-variation aware clocking have recently been shown to possess increased immunity to manufacturing process variations. In this article, we propose a theoretical framework that allows designers to quantify the performance improvement that is to be expected if they were to migrate from a fully synchronous design to the proposed multiple VFI design style. Specifically, we provide techniques to efficiently and accurately estimate the probability distribution of the execution rate (or throughput) of both single and multiple VFI systems under the influence of manufacturing process variations. Finally, using an MPEG-2 encoder benchmark, we demonstrate how the proposed analysis framework can be used by designers to make architectural decisions such as the granularity of VFI domain partitioning based on the throughput constraints their systems are required to satisfy.

Process-Driven Variability Analysis of Single and Multiple Voltage–Frequency Island Latency-Constrained Systems

The problem of determining bounds for application completion times running on generic systems comprising single or multiple voltage-frequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-process-driven variability. The approach provides an exact solution for the system-level timing yield in synchronous single-voltage (SSV) and VFI systems with an underlying tree-based topology and a tight upper bound for generic non-tree-based topologies. The results show that: 1) timing yield for the overall source-to-sink completion time for generic systems can be modeled in an exact manner for both SSV and VFI systems and 2) multiple-VFI latency-constrained systems can achieve up to two times higher timing yield than their SSV counterparts. The results are formally proven and are supported by experimental results on two embedded applications, namely, a software-defined radio and a Moving Pictures Expert Group 2 encoder.