Multiple-Valued Logic Networks Research Articles

Local Search with Probabilistic Modeling for Learning Multiple-Valued Logic Networks

This paper proposes a probabilistic modeling learning algorithm for the local search approach to the Multiple-Valued Logic (MVL) networks. The learning model (PMLS) has two phases: a local search (LS) phase, and a probabilistic modeling (PM) phase. The LS performs searches by updating the parameters of the MVL network. It is equivalent to a gradient decrease of the error measures, and leads to a local minimum of error that represents a good solution to the problem. Once the LS is trapped in local minima, the PM phase attempts to generate a new starting point for LS for further search. It is expected that the further search is guided to a promising area by the probability model. Thus, the proposed algorithm can escape from local minima and further search better results. We test the algorithm on many randomly generated MVL networks. Simulation results show that the proposed algorithm is better than the other improved local search learning methods, such as stochastic dynamic local search (SDLS) and chaotic dynamic local search (CDLS).

An Improved Local Search Learning Method for Multiple-Valued Logic Network Minimization with Bi-objectives

SUMMARY This paper describes an improved local search method for synthesizing arbitrary Multiple-Valued Logic (MVL) function. In our approach, the MVL function is mapped from its algebraic presentation (sumof-products form) on a multiple-layered network based on the functional completeness property. The output of the network is evaluated based on two metrics of correctness and optimality. A local search embedded with chaotic dynamics is utilized to train the network in order to minimize the MVL functions. With the characteristics of pseudo-randomness, ergodicity and irregularity, both the search sequence and solution neighbourhood generated by chaotic variables enables the system to avoid local minimum settling and improves the solution quality. Simulation results based on 2variable 4-valued MVL functions and some other large instances also show that the improved local search learning algorithm outperforms the traditional methods in terms of the correctness and the average number of product terms required to realize a given MVL function.

A Stochastic Dynamic Local Search Method for Learning Multiple-Valued Logic Networks

In this paper, we propose a stochastic dynamic local search (SDLS) method for Multiple-Valued Logic (MVL) learning by introducing stochastic dynamics into the traditional local search method. The proposed learning network maintains some trends of quick descent to either global minimum or a local minimum, and at the same time has some chance of escaping from local minima by permitting temporary error increases during learning. Thus the network may eventually reach the global minimum state or its best approximation with very high probability. Simulation results show that the proposed algorithm has the superior abilities to find the global minimum for the MVL network learning within reasonable number of iterations.

A Learning Multiple-Valued Logic Network that can Explain Reasoning

A Learning Multiple-Valued Logic Network that can Explain Reasoning

A learning multiple-valued logic network: algebra, algorithm, and applications

We propose a multiple valued logic (MVL) network with functional completeness and develop its learning capability. The MVL network consists of layered arithmetic piecewise linear processors. Since the arithmetic operations of the network are basically a wired sum and a piecewise linear operation, their implementations should be rather simple and straightforward. Furthermore, the MVL network can be trained by the traditional backpropagation algorithm directly. The algorithm trains the networks using examples and appears to be available for most MVL problems of interest.

Multiple-valued logic network using quantum-device-oriented superpass gates and its minimisation

A superpass-transistor (SPT) model is presented as a quantum-device candidate for future VLSI systems based on multiple-valued logic (MVL). A conceptual SPT structure based on the ideas of a lateral-resonant-tunnelling quantum-dot transistor (LQT) and a heterostructure FET is described. An important feature of the SPT is its capability of MVL signal detection and generation. A superpass gate (SP gate) corresponding to a single SPT is defined and is demonstrated to be a universal logic module for implementing highly compact multiple-valued VLSI systems. An algorithm suitable for synthesising minimal series-parallel SP-gate networks for MVL functions with many variables is proposed. The network allows both constants and variables as its pass inputs; accordingly, upsilon -subfunctions, where upsilon can be a constant or a variable, are defined. SP implicants, SP subimplicants and the consensus between SP subimplicants are also defined. The algorithm first generates all prime SP subimplicants from upsilon -subfunctions by using the consensus operation, then derives all prime SP implicants by using the implication operation, and finally selects an optimal set of prime SP implicants to cover the function by using existing methods.

Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module

This correspondence presents a theoretical study on the synthesis of multiple-valued logic networks based on tree-type universal logic modules (T-ULM's). The mathematical notation of T-ULM is introduced. On the basis of the mathematical properties, an algorithm for synthesizing an arbitrary logic function of n variables with a smaller number of modules is presented. In this algorithm, only true and constant inputs are allowed at input terminals. The algorithm consists of two parts. The first one is a functional decomposition, and the other one is the proper order of the expansion which is the problem of zinding the most incomplete tree structure. Thus it is established that the systematic and nonexhaustive procedure of the algorithm gives a suboptimal solution for the reduction of the number of T-ULM's.