Multiple Threads Of Execution Research Articles

Semantic web Racer: Dynamic security testing of the web application against race condition in the business layer

The parallel execution of multiple threads of a web application will cause races if the web application is not synchronized correctly. Detecting the race condition in web applications depends on the application’s business logic. No logic-aware approach has been presented so far for detecting various race conditions in web applications. The existing approaches only detect part of server-side races or a few client-side race conditions. Most existing approaches result in DoS or they have a high vulnerability detection time.In this study, various race conditions existing in a web application, both on the server-side and on the client-side, are classified and described. In addition, we present Semantic Web Racer, a black-box approach for dynamic application security testing, to detect the business-layer vulnerability of the web application against race conditions both on the server-side and on the client-side. Semantic Web Racer detects race conditions by identifying the business logic of the web application. First, it identifies the business processes in the web application and, by defining a trace pattern for each type of race condition, identifies critical business processes. The detected critical processes are performed in the defined race window in both normal mode and race-prone mode, and the results are checked to identify vulnerabilities.The evaluation of well-known and widely used web applications and web pages shows that Semantic Web Racer can detect the business layer vulnerabilities of these applications against race conditions. Experiments showed that out of 38 detected race conditions by Semantic Web Racer in selected applications, 24 are new vulnerabilities that were not identified by related works. The amount of traffic generated to identify vulnerabilities has been improved by about 98.29% by identifying the business layer of the application. Thus, Semantic Web Racer does not result in DoS. Semantic Web Racer has improved race detection time by about 96.78%.

Business-Layer Session Puzzling Racer: Dynamic Security Testing against Session Puzzling Race Conditions in the Business Layer

Parallel execution of multiple threads of a web application will result in server-side races if the web application is not synchronized correctly. Server-side race is susceptible to flaws in the relation between the server and the database. Detecting the race condition in the web applications depends on the business logic of the application. No logic-aware approach has been presented to deal with race conditions. Furthermore, most existing approaches either result in DoS or are not applicable with false positive. In this study, the session puzzling race conditions existing in a web application are classified and described. In addition, we present Business-Layer Session Puzzling Racer, a black-box approach for dynamic application security testing, to detect the business-layer vulnerability of the application against session puzzling race conditions. Experiments on well-known and widely used web applications showed that Business-Layer Session Puzzling Racer is able to detect the business layer vulnerabilities of these applications against race conditions. In addition, the amount of traffic generated to identify the vulnerabilities has been improved by about 94.38% by identifying the business layer of the application. Thus, Business-Layer Session Puzzling Racer does not result in DoS.

Energy Optimization by Software Prefetching for Task Granularity in GPU-Based Embedded Systems

Energy saving and optimization play an increasingly important role in industrial electronic systems. A heterogeneous embedded system is composed of a general-purpose central processing unit with an enhanced module of graphics processing units (GPU). This article explores the effective strategies of task granularity and software prefetching for energy optimization. In this article, we propose a novel energy optimization model for GPU-based embedded systems by harnessing a communication-based pipeline spatial and temporal relation. We analyze the characteristics of a multiple thread execution of parallel GPUs. We present an effective algorithm for the dynamic power optimization with the adaptively adjusted distance of software prefetching. The experimental results show that the dynamic energy consumption can be saved by 22.1% and 21.8%, respectively, under two prefetching strategies (register and shared memory) without loss of performance. We demonstrate the effectiveness of the proposed methods for energy saving and consumption reduction of performance driven computing in industrial scenarios.

Dynamic capping of rename registers for SMT processors

Abstract Simultaneous Multithreading improves performance of superscalar CPUs by allowing execution of multiple threads with a shared path. An improved instruction throughput is attained by better utilizing shared resources from exploiting the newly available thread-level parallelism in addition to the intrinsic instruction-level parallelism. Physical Register file is one of the most critical shared resources in SMT systems due to the limited number of rename registers available for renaming. Registers held by long-latency instructions of some threads will block the progress of other faster threads resulting in inefficient resource utilization and performance degradation. In this paper, we present an algorithm with which each thread is allotted a portion of rename registers (i.e. a cap) in real time according to their run-time behaviors, namely the utilization ratio of its allotted quota and the pace of its deallocation. The proposed method differs from the state-of-the-art capping techniques in allowing each thread to adjust its own individual cap value in real time. To preclude over-adjustment, a global lower limit on the cap values is further established also in real time to accommodate potentially drastic variations from different mixes of on-going threads. The proposed method shows a very significant improvement in IPC up to 53.8% in a 4-threaded system, 43.8% and 41.6% in a 6-threaded and an 8-threaded system respectively.

Toward data-driven architectural support in improving the performance of future HPC architectures

We propose architectures based on Data-Driven Multithreading (DDM), a hybrid control-flow/data-flow model, to address the concurrency challenges faced by future High-Performance Computing (HPC) systems. We focus on the design and implementation of an optimized hardware Thread Scheduling Unit (TSU) and its integration into a multi-core system dubbed MiDAS. The TSU is the core of the DDM model and it orchestrates the execution of multiple threads on sequential processors based on data availability. MiDAS was prototyped on a Xilinx Virtex-6 FPGA and extensively evaluated using several micro-benchmarks, showing that it achieves linearly-growing performance as the processing core count increases even when running benchmarks comprising very small problem sizes. Under the largest problem size tested and with all 8 available cores being utilized, MiDAS achieves an average speedup of 7.91×, exhibiting 98.8% utilization efficiency. Further, several results pertaining to the proposed hardware TSU are provided, including FPGA real estate requirements, where it is found that MiDAS’s TSU demands relatively small overheads and reduced power consumption, while various TSU operations adhere to low latency responses. To back said claims, the proposed DDM-based TSU is compared with the Task Superscalar architecture that implements the StarSs programming framework in hardware. As such, comparison results show that the proposed TSU requires much less of both hardware investment and energy consumption to operate. Specifically, Task Superscalar is found to be 4.94 × larger than the DDM-supporting TSU in terms of slice register requirements and 11.34 × larger with respect to the slice look-up table count. Last, the hardware TSU is compared with a software TSU implementation offering identical functionalities, with both being run on an FPGA fabric under a synthetic application, where a detailed performance evaluation shows that MiDAS’s hardware-implemented TSU significantly outperforms its software-based TSU counterpart.

SKIRT: Hybrid parallelization of radiative transfer simulations

We describe the design, implementation and performance of the new hybrid parallelization scheme in our Monte Carlo radiative transfer code SKIRT, which has been used extensively for modeling the continuum radiation of dusty astrophysical systems including late-type galaxies and dusty tori. The hybrid scheme combines distributed memory parallelization, using the standard Message Passing Interface (MPI) to communicate between processes, and shared memory parallelization, providing multiple execution threads within each process to avoid duplication of data structures. The synchronization between multiple threads is accomplished through atomic operations without high-level locking (also called lock-free programming). This improves the scaling behavior of the code and substantially simplifies the implementation of the hybrid scheme. The result is an extremely flexible solution that adjusts to the number of available nodes, processors and memory, and consequently performs well on a wide variety of computing architectures.

The Integer Nucleolus of Directed Simple Games: A Characterization and an Algorithm

We study the class of directed simple games, assuming that only integer solutions are admitted; i.e., the players share a resource that comes in discrete units. We show that the integer nucleolus—if nonempty—of such a game is composed of the images of a particular payoff vector under all symmetries of the game. This payoff vector belongs to the set of integer imputations that weakly preserve the desirability relation between the players. We propose an algorithm for finding the integer nucleolus of any directed simple game with a nonempty integer imputation set. The algorithm supports the parallel execution of multiple threads in a computer application. We also consider the integer prenucleolus and the class of directed generalized simple games.

Research on Cache Timing Attack Against RSA with Sliding Window Exponentiation Algorithm

The vulnerabilities of the RSA cryptographic algorithm are analyzed, and it is not securely implemented. As the simultaneous multithreading could enable multiple execution threads to share the execution resources of a superscalar between the chipper process and the spy process, the shared access to memory caches provides an easily used high bandwidth covert channel between threads, allowing that a malicious thread can monitor the execution of another thread. This paper targets at RSA algorithm which is implemented with sliding window exponentiation algorithm via OpenSSL, the attacker can monitor the cryptographic thread by executing a spy thread, recording the timing characteristic during the RSA decryption when reading the Cache. The attacker can recover the original key via analyzing these timing measurements. Finally, the authors provide some countermeasures of how this attack could be mitigated or eliminated entirely.

Research of three-dimensional dendritic growth using phase-field method based on GPU

The interface thickness of phase-field model limits its simulation scale. In order to shorten the computation time, the large undercooling degree higher than that under the conventional casting process condition is often employed in the three-dimensional dendritic growth simulation, and many qualitative simulations are mainly aimed at a single dendrite and multi-dendrites morphologies for pure substances or binary alloys. The problems of low computational efficiency, small-scale simulation and limited to qualitative research exist on a single CPU computation using phase-field method. To simulate microstructure evolution process during actual casting solidification more effectively, a high performance computing method based on CUDA+GPU architecture is explored in this paper, and larger-scale computation is implemented by the concurrent execution of multiple threads to improve computational efficiency. The three-dimensional dendritic growth of pure SCN is quantitatively simulated on a single GPU, and the computational efficiency based on a single GPU and a single CPU is also compared under the same condition. The simulation results show that a speedup of 98.52 is achieved when the grid size is 5123 on the GPU, with computational efficiency being greatly improved. Meanwhile, the calculated values of the dendritic tip velocities and the tip radius on the GPU are identical with the values of the microscopic solvability theory and the references’ simulation results, which validates the GPU parallel algorithm.

OpenGeoSys-Gem: A numerical tool for calculating geochemical and porosity changes in saturated and partially saturated media

Reactive transport codes that use a Gibbs Energy Minimization (GEM) to solve chemical equilibria are uncommon. We present a new coupling of the Richards flow module of the Finite Element (FE) based OpenGeoSys code with the GEM based chemical solver GEMS3K. The coupled code is highly parallelized using an overlapping domain decomposition approach in combination with execution of multiple threads that solve chemical equilibria in parallel. FE reactive transport schemes are often affected by spurious concentration oscillations. We effectively suppress these oscillations with a linearized algebraic flux corrected transport (FCT) algorithm. An application example is presented which investigates the evolution of material interfaces in a deep geological repository for nuclear waste. The example uses all features of the new coupled code: flow and multi-component transport in variably saturated media, and a very complex chemical setup which makes extensive use of (non-linear) solid solution formulations for mineral phases.

Multi-core job submission and grid resource scheduling for ATLAS AthenaMP

AthenaMP is the multi-core implementation of the ATLAS software framework and allows the efficient sharing of memory pages between multiple threads of execution. This has now been validated for production and delivers a significant reduction on the overall application memory footprint with negligible CPU overhead. Before AthenaMP can be routinely run on the LHC Computing Grid it must be determined how the computing resources available to ATLAS can best exploit the notable improvements delivered by switching to this multi-process model. A study into the effectiveness and scalability of AthenaMP in a production environment will be presented. Best practices for configuring the main LRMS implementations currently used by grid sites will be identified in the context of multi-core scheduling optimisation.

Fast parallel genetic programming: multi-core CPU versus many-core GPU

Genetic Programming (GP) is a computationally intensive technique which is also highly parallel in nature. In recent years, significant performance improvements have been achieved over a standard GP CPU-based approach by harnessing the parallel computational power of many-core graphics cards which have hundreds of processing cores. This enables both fitness cases and candidate solutions to be evaluated in parallel. However, this paper will demonstrate that by fully exploiting a multi-core CPU, similar performance gains can also be achieved. This paper will present a new GP model which demonstrates greater efficiency whilst also exploiting the cache memory. Furthermore, the model presented in this paper will utilise Streaming SIMD Extensions to gain further performance improvements. A parallel version of the GP model is also presented which optimises multiple thread execution and cache memory. The results presented will demonstrate that a multi-core CPU implementation of GP can yield performance levels that match and exceed those of the latest graphics card implementations of GP. Indeed, a performance gain of up to 420-fold over standard GP is demonstrated and a threefold gain over a graphics card implementation.

Cooperative and competitive concurrency in scientific computing. A full open-source upgrade of the program for dynamical calculations of RHEED intensity oscillations

Cooperative and competitive concurrency in scientific computing. A full open-source upgrade of the program for dynamical calculations of RHEED intensity oscillations

Understanding the behavior and implications of context switch misses

One of the essential features in modern computer systems is context switching, which allows multiple threads of execution to time-share a limited number of processors. While very useful, context switching can introduce high performance overheads, with one of the primary reasons being the cache perturbation effect. Between the time a thread is switched out and when it resumes execution, parts of its working set in the cache may be perturbed by other interfering threads, leading to (context switch) cache misses to recover from the perturbation. The goal of this article is to understand how cache parameters and application behavior influence the number of context switch misses the application suffers from. We characterize a previously unreported type of context switch misses that occur as the artifact of the interaction of cache replacement policy and an application's temporal reuse behavior. We characterize the behavior of these “reordered misses” for various applications, cache sizes, and various amount of cache perturbation. As a second contribution, we develop an analytical model that reveals the mathematical relationship between cache design parameters, an application's temporal reuse pattern, and the number of context switch misses the application suffers from. We validate the model against simulation studies and find that it is sufficiently accurate in predicting the trends of context switch misses with regard to various cache perturbation amount. The mathematical relationship provided by the model allows us to derive insights into precisely why some applications are more vulnerable to context switch misses than others. Through a case study on prefetching, we find that prefetching tends to aggravate the number of context switch misses and a less aggresive prefetching technique can reduce the number of context switch misses the application suffers from. We also investigate how cache sizes affect context switch misses. Our study shows that under relatively heavy workloads in the system, the worst-case number of context switch misses an application suffers from tends to increase proportionally with cache sizes, to the extent that may completely negate the reduction in other types of cache misses.

An events based algorithm for distributing concurrent tasks on multi-core architectures

In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application to a wide range of numerical simulation problems. Such problems involve time stepping or iteration algorithms where synchronization of multiple threads of execution is required. It is shown that traditional approaches to parallelism including message passing and scatter-gather can be improved upon in terms of speed-up and memory management. Using spatial decomposition to create orthogonal computational tasks, a new task management algorithm called H-Dispatch is developed. This algorithm makes efficient use of memory resources by limiting the need for garbage collection and takes optimal advantage of multiple cores by employing a hungry pull strategy. The technique is demonstrated on a simple finite difference solver and results are compared to traditional MPI and scatter-gather approaches. The H-Dispatch approach achieves near linear speed-up with results for efficiency of 85% on a 24-core machine. It is noted that the H-Dispatch algorithm is quite general and can be applied to a wide class of computational tasks on heterogeneous architectures involving multi-core and GPGPU hardware.

Accelerated gradient learning algorithm for neural network weights update

This work proposes decomposition of square approximation algorithm for neural network weights update. Suggested improvement results in alternative method that converge in less iteration and is inherently parallel. Decomposition enables parallel execution convenient for implementation on computer grid. Improvements are reflected in accelerated learning rate which may be essential for time critical decision processes. Proposed solution is tested and verified on multilayer perceptrons neural network case study, varying a wide range of parameters, such as number of inputs/outputs, length of input/output data, number of neurons and layers. Experimental results show time savings up to 40% in multiple thread execution.

Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency

Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today's processors, or the power dissipation will become prohibitive in all but water-cooled systems. Compounding these problems is the simple fact that with the immense numbers of transistors available on today's microprocessor chips, it is too costly to design and debug ever-larger processors every year or two. CMPs avoid these problems by filling up a processor die with multiple, relatively simpler processor cores instead of just one huge core. The exact size of a CMPs cores can vary from very simple pipelines to moderately complex superscalar processors, but once a core has been selected the CMPs performance can easily scale across silicon process generations simply by stamping down more copies of the hard-to-design, high-speed processor core in each successive chip generation. In addition, parallel code execution, obtained by spreading multiple threads of execution across the various cores, can achieve significantly higher performance than would be possible using only a single core. While parallel threads are already common in many useful workloads, there are still important workloads that are hard to divide into parallel threads. The low inter-processor communication latency between the cores in a CMP helps make a much wider range of applications viable candidates for parallel execution than was possible with conventional, multi-chip multiprocessors; nevertheless, limited parallelism in key applications is the main factor limiting acceptance of CMPs in some types of systems.

Redistribution in distributed Ada

In this paper we will demonstrate how Ada and its Distributed Annex may be used to relocate concurrent objects in a distributed dataflow application. This relocation mechanism will provide the capability of providing both passive and active fault tolerance. Special care will be taken to demonstrate how errors are trapped and propagated across partitions containing multiple threads of execution.

Performance evaluation of a commercial cache-coherent shared memory multiprocessor

This paper describes an approximate Mean Value Analysis (MVA) model developed to project the performance of a small-scale shared-memory commercial symmetric multiprocessor system. The system, based on Hewlett Packard Precision Architecture processors, supports multiple active user processes and multiple execution threads within the operating system. Using detailed timing for hardware delays, a customized approximate closed queueing model is developed for the multiprocessor system. The model evaluates delays due to bus and memory contention, and cache interference. It predicts bus bandwidth requirements and utilizations for the bus and memory controllers. An extension to handle I/O traffic is outlined. Applications are profiled on the basis of execution traces on uniprocessor systems to provide inputs parameters for the model. Performance effects of various detailed architectural tradeoffs (memory interleaving, lower memory latencies) are examined. The sensitivity of overall system performance to various parameters is explored. Preliminary measurements of uniprocessor systems are compared against the model predictions. A prototype multiprocessor system is under development. We intend to validate the modeling results against measurements.

Synchronised execution on shared memory multiprocessors

Threads provides a mechanism for simulating the execution of parallel algorithms on a simplified model of a shared-memory multiprocessor. The algorithms can be expressed in a high-level block-structured language, which supports multiple threads of execution within a common body of program code. Results show an ability to achieve good speedup for small problems using algorithms derived by simple modifications of sequential algorithms. As well, a sibling thread synchronisation feature provides the basis for the synchronous execution of threads. k-parallel algorithms tailored to the machine size and implemented as synchronously executing iterations, can provide near linear speedup as the problem size is increased. The techniques described in this paper seem to promise an effective synchronous execution mode for shared-memory MIMD architectures.