Multiple Printed Circuit Boards Research Articles

Circulating and Eddy Current Losses in Coreless Axial Flux PM Machine Stators With PCB Windings

Printed circuit board (PCB) stators in coreless axial flux permanent magnet (AFPM) machines have been proposed, designed, and studied for use in multiple industries due to their design flexibility and reduction of manufacturing costs, volume, and weight compared to conventional stators. This paper investigates mechanisms and methods of approximating open circuit losses in PCB stators within example wave and spiral winding topologies for a dual rotor, single stator configuration using 3D FEA, analytical hybrid techniques and experiments. The effect of rotor magnet shape, end winding, and active conductor geometry on eddy currents is studied, and some mitigation techniques are proposed. Through stator equivalent circuit analysis, circulating current losses caused by mechanical abnormalities and magnetic circuit asymmetry are assessed. Possible strategies and schemes to minimize circulating current losses are also described. The trade-off between stator loss components and some practical design considerations are outlined in detail. The open circuit power losses of a prototype coreless AFPM motor were experimentally tested using multiple example PCB stators and emulated rotor asymmetries, with the findings being comparable to the FEA and hybrid analytical methods results.

Disposable platform for bacterial lysis and nucleic acid amplification based on a single USB-powered printed circuit board.

Recent advances in electronics and microfluidics have enabled several research groups to develop fully integrated, sample-to-result isothermal nucleic acid amplification test (NAAT) platforms for the point of care. However, high component counts and costs have limited translation of these platforms beyond the clinic to low-resource settings-including homes. Many NAATs include complex, multi-component heater electronics based on flex circuits or multiple printed circuit boards (PCBs) to support essential NAAT steps such as lysis, sample deactivation, and nucleic acid amplification. In contrast, current commercial assays for home use, such as those for pregnancy or ovulation that include electronics, typically have just one onboard PCB. This work describes a generalizable strategy to integrate all heaters and the electronics needed to control them onto a single low-cost, USB-powered PCB. We built a multiplexable disposable NAAT ("MD NAAT") platform that applies these principles, integrating small-area heaters that heat small regions to near-boiling (for pathogen lysis and deactivation) and large-area heaters (for amplification) on the same PCB. We show that both classes of heaters have high intra-board and inter-device reproducibility despite only heating a NAAT cartridge from below. We validated the small-area heaters by lysing methicillin-resistant Staphylococcus aureus (MRSA) cells and the large-area heaters by performing two types of isothermal NAATs (isothermal strand displacement amplification (iSDA) and loop-mediated isothermal amplification (LAMP)). These results demonstrate the merit of integrating NAAT heaters and control electronics onto a single printed circuit board and are a step toward translating NAATs to the home.

New Products

Keysight Technologies, Inc. has introduced the new i7090 massively parallel board test system. This is a new category of automated test equipment designed to perform tests in parallel, on multiple printed circuit board assemblies (PCBA), to achieve high volume throughput which speeds time-to-market and reduces cost-of-test.

A High-Gain Millimeter-Wave Magnetoelectric Dipole Array With Packaged Microstrip Line Feed Network

A millimeter-wave 4 × 4 magnetoelectric (ME) dipole antenna array using a packaged microstrip line feed network is proposed. This antenna array features a wide impedance bandwidth of more than 50% and small back radiation. Each ME dipole element is excited by an L -shaped probe and each L -shaped probe is connected to the packaged microstrip line through a small hole in the ground plane. The packaged microstrip line forms the whole corporate feed network for the antenna array. The entire antenna structure is realized by multiple printed circuit boards (PCBs), which is low in material cost and easy in fabrication. The results demonstrate that the proposed antenna array enables the impedance bandwidth of 51.5%, high gain up to 20.3 dBi, and stable broadside radiation pattern with small back radiation over the operating frequencies. The array is suitable for the 5G application.

An artificial dielectric slab for ultra high-field MRI: Proof of concept

High-permittivity dielectric pads, i.e., thin, flexible slabs, usually consisting of mixed ceramic powders and liquids, have been previously shown to increase the magnetic field at high and ultra high-fields in regions of low efficiency of transmit coils, thus improving the homogeneity of images. However, their material parameters can change with time, and some materials they contain are bio incompatible. This article presents an alternative approach replacing ceramic mixtures with a low-cost and stable artificial dielectric slab. The latter comprises a stack of capacitive grids realized using multiple printed-circuit boards. Results in this article show that the proposed artificial dielectric structure can obtain the same increase in the local transmit radiofrequency magnetic field distribution in a head phantom at 7 T as the conventional dielectric pad.

Atmospheric-Like Neutron Attenuation During Accelerated Neutron Testing With Multiple Printed Circuit Boards

Engineers usually test multiple printed circuit boards (PCBs) and integrated circuits (ICs) in the neutron beam to improve the error statistics. The attenuation of an atmospheric-like neutron spectrum by materials commonly used in PCBs is evaluated experimentally and with simulations of the neutron transport. Measurements were performed during neutron irradiation experiments of multiple boards using a beam monitor to correlate simulations with experimental results.

Vibration Analysis of Printed Circuit Board Plate with Varying Boundary Conditions

Objectives: The Young’s Modulus (E) plays key role in the vibration response of any structure. Hence its estimate with reasonable accuracy is of paramount importance. The Printed Circuit Board (PCB) used in military application consists of more than 6 layers, with pre-peg and copper composition. Methods/Statistical Analysis: The multiple layers PCB E value will vary from one design to other as it depends on the composition of layers. These PCB plates are subjected to vibration loads – sine, random and shock. A detailed work has been carried out to quantify the mechanical property of Young’s Modulus (E) of the PCB plate both analytically and experimentally. Findings: This E value obtained was used in the FEM analysis (using ANSYS 16) to solve the vibration response of the PCB. The study also includes analytical calculation and experimental estimation of natural frequency of the PCB plate for different boundary conditions. The natural frequency estimation through analytical and experimental methods show good correlation thus validating the estimation procedure of E of the PCB as well. Application: This work gives us a robust method for estimating Young’s modulus of Multi-layer PCB which find application in variety of military electronics.

Lagrangian approach to minimize makespan of non-identical parallel batch processing machines

This research is motivated by the testing operations conducted at an electronics manufacturing facility. Printed Circuit Boards (PCBs) of varying size are assembled on multiple assembly lines. The PCBs from different assembly lines are later grouped to form batches that are scheduled for testing on non-identical Environmental Stress Screening (ESS) chambers. The ESS chambers can process multiple PCBs simultaneously as long as the total size of all PCBs in the batch does not exceed the chamber’s capacity. The testing time of the batch depends on the composition of the batch. The chambers are referred to as Batch Processing Machines (BPMs) and PCBs are jobs in this paper. Scheduling non-identical BPMs to minimize the makespan objective is known to be NP-hard. Consequently, the Particle Swarm Optimization (PSO) and Random Keys Genetic Algorithm (RKGA) approaches were proposed in the literature. In this research, a Lagrangian Relaxation (LR) approach is proposed. The solution from the LR approach is compared to the solution from PSO, RKGA, and a commercial solver. An experimental study is conducted on benchmark instances and the LR approach identified a new improved solution for several problem instances.

A Computable Model for PCB Assembly Optimization Based on Polychromatic Sets

A modeling methodology is presented for printed circuit board(PCB) assembly optimization based on polychromatic sets(PS) theory. A computable model framework with hierarchical structure includes three layers, which are set layer(SL), logic layer(LL) and numerical layer(NL). Based on the hierarchical model and the mapping relationship among each layer, a computable model is formulated to describe the PCB assembly optimization problem in multiple PCB assembly tasks and multiple machines. The computable model not only involves various computation parameters, complicate constraint relationships such as process constraints, resource constraints and so on in PCB assembly optimization, but also describes the shortage of component, machine failure, order change and other uncertain factors. The optimization problems of PCB assembly in low-volume environment and multiple tasks can be solved efficiently.

Mechanical Stress Analysis and Evaluation of Hybrid Land Grid Array Attached Large Form Factor Organic Modules

Recent industry trends to continue enabling increased server system performance and packaging density has driven the need to implement larger form factor hybrid land grid array (LGA) attached organic modules. In addition, given the need to package multiple modules on a single printed circuit board (PCB) assembly, PCB cross-sections and their corresponding physical properties (e.g., flatness, etc.) as well as module bottom surface metallurgy (BSM) co-planarity require a more detailed understanding of impacts to the compliant as well as the soldered connector interfaces. Lastly, the migration to lead (Pb)-free solders has further complicated the issue given both the change in material properties as well as processing temperatures. In this paper we will discuss the mechanical stress analysis and evaluation tests assessment of a recently developed 50 mm square organic processor module, hybrid LGA attached to a multiple site PCB. The analysis presented will highlight the methodology to identify both connector soldered stress and predicted contact load variation across the module's mated interface. Key parameters discuss will include the PCB flatness, Organic substrate BSM co-planarity (both predicted and measured) and the Hybrid LGA as-soldered contact co-planarity. Corroborating predicted analytical results, we will discuss various evaluation tests performed to validate the design's integrity. Key tests include, pressure sensitive film (PSF) studies and environment stress exposures, including thermal shock, mechanical shock and vibration and seismic exposure. Post test electrical integrity and test sample construction analysis, including 3D x-ray and mechanical cross-section, will also be described. The analysis process and testing described will provide a method to evaluate more challenging hybrid LGA applications as both module sizes and/or number applied per PCB assembly increase and Pb-free assembly is introduced in future applications.

XTRONIC®: Enabler of Improved Performance with Reduced Precious Metal Usage in Microelectronics

XTRONIC®, a tailored nanocrystalline nickel alloy, has been qualified as a new metal barrier layer replacing pure nickel in many traditional hard and soft gold applications. XTRONIC is produced using a proprietary combination of electroplating chemistry and pulse-reverse applied current waveforms that enables dynamic control of the deposited material's composition and grain structure. The resulting deposits have been shown to provide superior performance in a variety of areas that are critical to microelectronics. These improved performance metrics include resistance to corrosive environments, wear durability, wire bonding, and temperature aging performance. The novel suites of properties possible provide enhanced performance for microelectronics, and can also enable equivalent or improved overall performance even with significant reductions of precious metal use in many applications. Proven areas of application include high-speed backplane connectors and multiple printed circuit board applications such as dual in-line memory module (DIMM) and flash memory card (FMC) applications. In the current paper we focus on properties for printed circuit board applications.

A particle swarm optimization algorithm for minimizing makespan of nonidentical parallel batch processing machines

This research is motivated by our interactions with an electronics manufacturer who assembles and tests printed circuit boards (PCBs) used in consumer products. Environmental stress screening (ESS) chambers are commonly used to test PCBs to detect early failures before they are used in the field. The chambers are capable of testing multiple PCBs simultaneously (i.e., batch processing machines). The minimum testing time of each PCB and their size are known. The objective is to group these PCBs into batches and schedule the batches formed on ESS chambers such that the makespan is minimized. The ESS chambers can process a batch of jobs as long as its capacity is not violated. Each ESS chamber is unique with respect to its capacity. The problem is NP-hard. Consequently, a particle swarm optimization (PSO) algorithm is proposed. The effectiveness of the PSO algorithm is evaluated by comparing its results to a random-key genetic algorithm and a commercial solver used to solve a mixed-integer linear program. A thorough experimental study conducted indicates that the PSO algorithm reports better quality solution in a short time on larger problem instances.

An Efficient and Cost-Saving Component Scheduling Algorithm Using High Speed Turret Type Machines for a Board Containing Multiple PCBs

This paper considers a material constrained component scheduling problem during the high speed surface mount manufacturing stage in printed circuit board (PCB) assembly, where each piece of board contains an even number of identical PCBs. To accomplish the production, material requirements must be predetermined and incorporated as restraints into the scheduling problem, which has the objective of minimizing production completion time (makespan). A solution procedure is developed based on the following strategies: 1) Each machine is responsible for the same PCBs of each piece, 2) Components of the same types may use one or more feeder locations, 3) Component types are clustered based on their suitable placement speeds, 4) A heuristic using a bottom-up approach is applied to determine the component placement sequence and the feeder location assignment for all machines. Velocity estimate functions of the turret, XY table, and feeder carriage were derived based on empirical data. An experiment using Fuji CP732E machines was conducted on two real life instances. Experimental results indicate that our method performs 32.96% and 10.60% better than the Fuji-CP software for the two instances, in terms of the makespan per piece of board.

Novel strategies of bioleaching metals from printed circuit boards (PCBs) in mixed cultivation of two acidophiles

Effects of two acidophiles on metals recovery in printed circuit boards (PCBs) were investigated. Based on the phenomenon that PCBs addition times and amounts adversely inhibited bacterial growth and thus lowered metals bioleaching capacity, novel strategies of multiple PCBs additions (4 g/l at 48 h, 6 g/l at 96 h and 8 g/l at 144 h) were developed in separated culture of Acidithiobacillus thiooxidans and Acidithiobacillus ferrooxidans. As a result, percentages of Cu, Ni, Zn and Pb leached by A. thiooxidans were 78, 73, 75 and 71%, and corresponding values were 80, 73, 76 and 72% by A. ferrooxidans after 240 h cultivation. Further applying the strategies to mixed culture of two acidophiles, extraction percentages of Cu, Ni, Zn and Pb were 94, 89, 90 and 86%, respectively. Moreover, increased redox potential and lowered pH in filtrate were observed, suggesting the mechanism involved in enhancing metals recovery in mixed culture.

Optimization of Printed Circuit Board Assignment and Component Allocation in Assembly Line

The assembly optimization problem of multiple printed circuit board (PCB) tasks is analyzed, and an optimal model is formulated to balance the workload in decoupled PCB assembly line. Combined with polychromatic sets and genetic algorithm (GA), an integrated methodology is developed to solve the PCB assignment and component allocation simultaneously. Based on polychromatic sets theory, a 3D numerical contour matrix is presented to describe the characters of PCB, component and machine and the constraint of machine and process, and a constraint model is formulated. Constraint model guarantees that GA searches in the available solution space and simplify the calculation of fitness value and GA operation. Computational results indicate that the approach presented in this paper is useful and effective.

Dual-side and three-dimensional microelectrode arrays fabricated from ultra-thin silicon substrates

A method for fabricating planar implantable microelectrode arrays was demonstrated using a process that relied on ultra-thin silicon substrates, which ranged in thickness from 25 to 50 µm. The challenge of handling these fragile materials was met via a temporary substrate support mechanism. In order to compensate for putative electrical shielding of extracellular neuronal fields, separately addressable electrode arrays were defined on each side of the silicon device. Deep reactive ion etching was employed to create sharp implantable shafts with lengths of up to 5 mm. The devices were flip-chip bonded onto printed circuit boards (PCBs) by means of an anisotropic conductive adhesive film. This scalable assembly technique enabled three-dimensional (3D) integration through formation of stacks of multiple silicon and PCB layers. Simulations and measurements of microelectrode noise appear to suggest that low impedance surfaces, which could be formed by electrodeposition of gold or other materials, are required to ensure an optimal signal-to-noise ratio as well a low level of interchannel crosstalk.

Modeling and Simulation of Electronic Packages Subjected to Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers, especially for handheld electronic products. These handheld electronic products are more prone to being dropped during their useful service life because of their small size and light weight. The electronic packages used in portable devices are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The dropping events not only induce mechanical failures in the housing of the device, but also lead to failure of PCB and components mounted on it. This work deals with: (a) Development of a simulation model of complete drop block with printed circuit board and plastic ball grid array (PBGA) assembly, which resembles actual drop test (free fall); (b) Development of an Input-G method for simulating the PCB dynamic responses; and (c) Comparison of results of free fall and Input-G methods. From the simulation results it was found that the mechanical shock causes multiple PCB bending and induce stresses in the solder balls of PBGA package. The solder balls at the outer rows of the PBGA package were subjected to maximum stress. Comparison of free fall drop and Input-G method results revealed that, the Input-G method uses less computer memory, takes less time to solve and it is simple to simulate the drop process.

Dynamic responses and solder joint reliability under board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. In this paper, the comprehensive dynamic responses of printed circuit boards (PCBs) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. Control and monitoring of dynamic responses are very important to ensure consistent test results and understand the mechanical behaviors, as they are closely related to the solder joint failure mechanism. The effects of test variables, such as drop height, number of PCB mounting screws, tightness of screws, and number of felt layer, are studied by comparing and analyzing the dynamic responses. A good repeatability of testing can only be achieved when careful attentions are paid on these factors. The relationships among drop height, peak acceleration, pulse duration, and impact energy are unique for a drop tester, and therefore, it should be characterized prior to the reliability tests. The studies also help to determine the requirements of new impact pulse quickly. The bending mode shapes and frequencies of PCB are extracted from dynamic strains and images token by high-speed camera. A real-time dynamic resistance monitoring method is developed to study the solder joint reliability. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint crack failure. Cyclic changes of dynamic resistance indicate that the solder joint crack opens and closes when PCB bends up and down.

Advanced Numerical and Experimental Techniques for Analysis of Dynamic Responses and Solder Joint Reliability During Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e., crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints, dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when the PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross section and dye penetration tests

BladeCenter midplane and media interface card

This paper describes the electrical architecture and design of the IBM eServerTM BladeCenter® midplane and media interface card. The midplane provides the redundant interconnects among processor blades, switch modules, media interface card, and management modules. It also serves as the redundant power distribution medium from the power modules to all blades and other devices. A major attribute of the BladeCenter electrical design is the redundant nature of the interconnects, which gives this product superior reliability and availability. The media interface card provides the interface between the CD-ROM and floppy disk drives and the blades that share these devices. The sharing of these devices was a key BladeCenter innovation. Also, to ensure that the architecture will be flexible enough to support multiple input/output fabric protocols, SerDes (serialized/deserialized) is used as the internal high-speed communication electrical interface. Since high-speed designs can easily result in higher implementation costs, a significant predesign simulation effort was undertaken to analyze and prioritize design guidelines in order to develop a high-speed midplane at a competitive cost. This paper highlights how we reduced board costs by finding solutions that overcame some of the challenges of 2.5-Gb/s data transmission over multiple printed circuit boards and connectors.