Multiple Parametric Faults Research Articles

Integer Algorithm: A Useful Tool for Fault Diagnosis of Analog Circuits

This paper presents an efficient numerical method to solve systems of nonlinear algebraic equations. The method uses a homotopy simplicial approach associated with an integer algorithm. The integer algorithm is discussed in detail and supplemented with original procedures that play an essential role during computation. The fundamental problem of initial simplex generation was solved using the bounded variable simplex optimization method. Efficient root finding of nonlinear equations has wide applications in numerical mathematics and various engineering problems. The proposed method was applied to solve nonlinear equations that arise during the diagnostics of multiple parametric faults in electronic circuits. Circuits made with surface mount technology were considered, as well as circuits designed in complementary metal-oxide-semiconductor and bipolar technology. A universal diagnostic procedure enables testing different circuit classes using standard measurement equipment. Laboratory and numerical experiments demonstrate that the proposed diagnostic procedure is effective.

Multiple parametric faults diagnosis for power electronic circuits based on hybrid bond graph and genetic algorithm

Abstract Aiming at the problem to diagnosis multiple parametric faults in power electronic circuits, a new diagnosis framework based on hybrid bond graph (HBG) and genetic algorithm (GA) is presented. Firstly, the circuits are modeled by HBG modeling technique, in which the equivalent models of the key components are considered. Then, a set of residuals equations and a fault signature matrix (FSM) are derived from the HBG model. Each faulty component exhibits their degradation symptoms on residuals equations. Thus, faults can be detected by comparing residuals with fault detection thresholds and isolated based on FSM. Finally, GA method is employed to identify the component faults. The fitness function of GA is constructed by the residuals equations in which the faulty components are contained. Simulation and experiment are carried out to verify the feasibility and effectiveness. The results show that the developed method is applicable to diagnosis both single and multiple parametric faults.

Multi‐class classification using kernel density estimation on K ‐nearest neighbours

A fast and accurate multi-class classification method based on the conventional kernel density estimation (KDE) and K-nearest neighbour (KNN) techniques is proposed. This method estimates the cumulative probabilities of the test sample on its KNNs which may belong to different classes, then selects the maximum weighted class as the classification result. Experiments are carried out to diagnose multiple parametric faults in an analogue circuit, and the classification performances of the proposed method as well as KNN, KDE and support vector machine are compared with each other in detail. The results show that the proposed method is generally better than the other methods not only in classification accuracy but also in test speed, and is promising for practical use.

A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits

This paper proposes a static linear behavior (SLB) analog fault model for switched-capacitor (SC) circuits. The SC circuits under test (CUT) are divided into functional macros including the operational amplifiers, the capacitors, and the switches. Each macro has specified design parameters from the design's perspectives. These design parameters constitute a parameter set which determines the practical transfer function of the CUT. The SLB fault model defines that a CUT is faulty if its parameter set results in transfer functions whose frequency responses are out of the design specification. We analyzed the fault effects of the macros and derived their faulty signal-flow graph models with which the faulty transfer function templates of the CUT can be automatically generated. Based on the templates, we proposed a test procedure that can estimate all the parameters in the parameter set so as to test the CUT with multiple faults. Different from conventional single fault assumption, the proposed SLB fault model covers concurrent multiple parametric faults and catastrophic faults. In addition, it does not need to conduct fault simulations before test as conventional analog fault models do. As a result, it addresses the impractically long fault simulation time issue. A fully-differential low-pass SC biquad filter was adopted as an example to demonstrate how to design and use efficient multitone tests to test for the parameter set. The multitone test results acquired during the test procedure also reveal the distortion and noise performance of the CUT though the SLB fault model does not include them.

DFT for digital detection of analog parametric faults in SC filters

Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude greater than that offered by any other DFT scheme reported in the literature.