Multiple Levels Of Parallelism Research Articles

FPGA-Based Updatable Packet Classification Using TSS-Combined Bit-Selecting Tree

OpenFlow switches are being deployed in SDN to enable a wide spectrum of non-traditional applications. As a promising alternative to brutal force TCAMs, FPGA-based packet classification is being actively investigated. However, none of the existing FPGA designs can achieve high performance on both search and update for large-scale rule sets. To address this issue, we propose TcbTree, an FPGA-based algorithmic scheme for packet classification. Specifically, at the algorithmic side, i) a two-stage framework consisting of heterogeneous algorithms is proposed, where most rules can be mapped into several balanced trees without rule replications, ii) for the remaining few rules, a centralized TSS (Tuple Space Search) architecture together with a real-time feedback scheme is designed to enhance the efficiency of TSS search on FPGA, and iii) a tree dilution method is designed to equalize rule distribution in trees, so that the latency of tree search can be reduced. At the hardware side, i) an efficient data structure set is designed to convert tree traversal to addressing process, which breaks the constraints of limited tree depth and imbalanced node distribution, and ii) distinct from fully pipelined designs, multiple levels of parallelism are efficiently explored with multi-core, multi-search-engine and coarse-grained pipelines herein. Experimental results using ClassBench show that, with the implementation of TcbTree on FPGA, the average classification throughputs for 1k, 10k, 32k and 100k rule sets achieve 788.8 MPPS, 404.3 MPPS, 237 MPPS and 41.8 MPPS, respectively, and the update throughput for all benchmark rule sets is above 1 MUPS.

A Reconfigurable and Pipelined Architecture for Standard-Compatible LDPC and Polar Decoding

With low-density parity-check (LDPC) codes and polar codes selected as the standard codes for the fifth generation (5G) enhanced Mobile Broad Band scenario (eMBB), a decoding architecture that can simultaneously support the decoding of control and data plane becomes necessary at the terminal side to meet the raising requirement for 5 G network deployment. Due to the special structure of LDPC codes according to the Release 15 (R15) 5G standard, a straight-forward extension of the existing reconfigurable scheme is in general difficult. Therefore in this paper, a unified decoding architecture is proposed that can be reconfigured to either LDPC codes or polar codes. Due to various differences between the two codes such as parity-check matrices, codeword lengths and iterative methods, a joint decoding algorithm is introduced by reordering basic decoding operations to the unified add-comparison-add pattern for both codes. Then, a pipelined structure of reconfigurable decoding unit (RDU) is presented correspondingly which is fully compatible with all decoding patterns of the R15 standard. And finally, a reconfigurable decoder is proposed with multiple levels of parallelism, and the reconfiguration scheme is introduced to improve the hardware utilization and decoding efficiency. The proposed decoder is implemented in FPGA and ASIC, respectively, and has achieved state-of-the-art performance in throughput and area efficiency compared to LDPC-only and polar-only decoders.

E3NE: An End-to-End Framework for Accelerating Spiking Neural Networks with Emerging Neural Encoding on FPGAs

Compiler frameworks are crucial for the widespread use of FPGA-based deep learning accelerators. They allow researchers and developers, who are not familiar with hardware engineering, to harness the performance attained by domain-specific logic. There exists a variety of frameworks for conventional artificial neural networks. However, not much research effort has been put into the creation of frameworks optimized for spiking neural networks (SNNs). This new generation of neural networks becomes increasingly interesting for the deployment of AI on edge devices, which have tight power and resource constraints. Our end-to-end framework E3NE automates the generation of efficient SNN inference logic for FPGAs. Based on a PyTorch model and user parameters, it applies various optimizations and assesses trade-offs inherent to spike-based accelerators. Multiple levels of parallelism and the use of an emerging neural encoding scheme result in an efficiency superior to previous SNN hardware implementations. For a similar model, E3NE uses less than 50\% of hardware resources and 20\% less power, while reducing the latency by an order of magnitude. Furthermore, scalability and generality allowed the deployment of the large-scale SNN models AlexNet and VGG.

Real-Time Scheduling and Analysis of OpenMP DAG Tasks Supporting Nested Parallelism

OpenMP is a promising framework to develop parallel real-time software on multi-cores. Although similar to the DAG task model, OpenMP task systems are significantly more difficult to analyze due to constraints posed by OpenMP specifications. One of the most interesting features in OpenMP is the support for nested parallelism, enjoying benefits in enhancing performance transparency of parallel libraries and promoting reuse of black-box code. Previous researches on DAG task scheduling mainly restrict to only one level of parallelism. The problem whether OpenMP tasks with multiple levels of parallelism are suitable to real-time systems remains open. In this paper, we study the real-time scheduling and analysis of OpenMP task systems supporting nested parallelism. First, we show that under existing scheduling algorithms in OpenMP implementations, nested parallelism indeed may lead to extremely bad timing behaviors where the parallel workload is sequentially executed completely. To solve this problem, we propose a new scheduling algorithm and develop two sound response time bounds by considering the trade-off between simplicity and analysis precision. Experiments demonstrate the efficiency of our methods.

The PHY-NGSC-Based ORT Run Length Encoding Scheme for Video Compression

This paper proposes a compression algorithm using octonary repetition tree (ORT) based on run length encoding (RLE). Generally, RLE is one type of lossless data compression method which has duplication problem as a major issue due to the usage of code word or flag. Hence, ORT is offered instead of using a flag or code word to overcome this issue. This method gives better performance by means of compression ratio, i.e. 99.75%. But, the functioning of ORT is not good in terms of compression speed. For that reason, physical- next generation secure computing (PHY-NGSC) is hybridized with ORT to raise the compression speed. It uses an MPI-open MP programming paradigm on ORT to improve the compression speed of encoder. The planned work achieves multiple levels of parallelism within an image such as MPI and open MP for parallelism across a group of pictures level and slice level, respectively. At the same time, wide range of data compression like multimedia, executive files and documents are possible in the proposed method. The performance of the proposed work is compared with other methods like accordian RLE, context adaptive variable length coding (CAVLC) and context-based arithmetic coding (CBAC) through the implementation in Matlab working platform.

WaLBerla: A block-structured high-performance framework for multiphysics simulations

Programming current supercomputers efficiently is a challenging task. Multiple levels of parallelism on the core, on the compute node, and between nodes need to be exploited to make full use of the system. Heterogeneous hardware architectures with accelerators further complicate the development process. waLBerla addresses these challenges by providing the user with highly efficient building blocks for developing simulations on block-structured grids. The block-structured domain partitioning is flexible enough to handle complex geometries, while the structured grid within each block allows for highly efficient implementations of stencil-based algorithms. We present several example applications realized with waLBerla, ranging from lattice Boltzmann methods to rigid particle simulations. Most importantly, these methods can be coupled together, enabling multiphysics simulations. The framework uses meta-programming techniques to generate highly efficient code for CPUs and GPUs from a symbolic method formulation.

A Holistic Scalable Implementation Approach of the Lattice Boltzmann Method for CPU/GPU Heterogeneous Clusters

Heterogeneous clusters are a widely utilized class of supercomputers assembled from different types of computing devices, for instance CPUs and GPUs, providing a huge computational potential. Programming them in a scalable way exploiting the maximal performance introduces numerous challenges such as optimizations for different computing devices, dealing with multiple levels of parallelism, the application of different programming models, work distribution, and hiding of communication with computation. We utilize the lattice Boltzmann method for fluid flow as a representative of a scientific computing application and develop a holistic implementation for large-scale CPU/GPU heterogeneous clusters. We review and combine a set of best practices and techniques ranging from optimizations for the particular computing devices to the orchestration of tens of thousands of CPU cores and thousands of GPUs. Eventually, we come up with an implementation using all the available computational resources for the lattice Boltzmann method operators. Our approach shows excellent scalability behavior making it future-proof for heterogeneous clusters of the upcoming architectures on the exaFLOPS scale. Parallel efficiencies of more than 90 % are achieved leading to 2604.72 GLUPS utilizing 24,576 CPU cores and 2048 GPUs of the CPU/GPU heterogeneous cluster Piz Daint and computing more than 6.8 × 10 9 lattice cells.

Modern gyrokinetic particle-in-cell simulation of fusion plasmas on top supercomputers

The gyrokinetic toroidal code at Princeton (GTC-P) is a highly scalable and portable particle-in-cell (PIC) code. It solves the 5-D Vlasov–Poisson equation featuring efficient utilization of modern parallel computer architectures at the petascale and beyond. Motivated by the goal of developing a modern code capable of dealing with the physics challenge of increasing problem size with sufficient resolution, new thread-level optimizations have been introduced as well as a key additional domain decomposition. GTC-P’s multiple levels of parallelism, including internode 2-D domain decomposition and particle decomposition, as well as intranode shared memory partition and vectorization, have enabled pushing the scalability of the PIC method to extreme computational scales. In this article, we describe the methods developed to build a highly parallelized PIC code across a broad range of supercomputer designs. This particularly includes implementations on heterogeneous systems using NVIDIA GPU accelerators and Intel Xeon Phi (MIC) coprocessors and performance comparisons with state-of-the-art homogeneous HPC systems such as Blue Gene/Q. New discovery science capabilities in the magnetic fusion energy application domain are enabled, including investigations of ion–temperature–gradient driven turbulence simulations with unprecedented spatial resolution and long temporal duration. Performance studies with realistic fusion experimental parameters are carried out on multiple supercomputing systems spanning a wide range of cache capacities, cache-sharing configurations, memory bandwidth, interconnects, and network topologies. These performance comparisons using a realistic discovery-science-capable domain application code provide valuable insights on optimization techniques across one of the broadest sets of current high-end computing platforms worldwide.

Towards the optimization of a gyrokinetic Particle-In-Cell (PIC) code on large-scale hybrid architectures

With the aim of enabling state-of-the-art gyrokinetic PIC codes to benefit from the performance of recent multithreaded devices, we developed an application from a platform called the “PIC-engine” [1, 2, 3] embedding simplified basic features of the PIC method. The application solves the gyrokinetic equations in a sheared plasma slab using B-spline finite elements up to fourth order to represent the self-consistent electrostatic field. Preliminary studies of the so-called Particle-In-Fourier (PIF) approach, which uses Fourier modes as basis functions in the periodic dimensions of the system instead of the real-space grid, show that this method can be faster than PIC for simulations with a small number of Fourier modes. Similarly to the PIC-engine, multiple levels of parallelism have been implemented using MPI+OpenMP [2] and MPI+OpenACC [1], the latter exploiting the computational power of GPUs without requiring complete code rewriting. It is shown that sorting particles [3] can lead to performance improvement by increasing data locality and vectorizing grid memory access. Weak scalability tests have been successfully run on the GPU-equipped Cray XC30 Piz Daint (at CSCS) up to 4,096 nodes. The reduced time-to-solution will enable more realistic and thus more computationally intensive simulations of turbulent transport in magnetic fusion devices.

Solving Random Ordinary Differential Equations on GPU Clusters using Multiple Levels of Parallelism

Random ordinary differential equations (RODEs) perfectly describe classes of time-dependent problems with stochastic disturbances that are of utmost importance in science and engineering. Both their pathwise solution concept leading to a massive amount of simulations and the form of the numerical solvers for RODEs contain high potential for efficient parallelization approaches. We analyze for the first time a high performance computing parallelization relying on GPU clusters to exploit the underlying three levels of parallelism for the example of the Kanai--Tajimi earthquake model in its RODE form. We identify four basic building blocks of the application which are valid also for general RODE scenarios. We optimized and benchmarked the implementation of the four building blocks separately to be able to select the best individual parameter settings. This allows for a comparison of the total performance of the overall application which shows excellent scaling results also on large GPU clusters. The results can be generalized to both other RODE applications and other approaches relying on a parallel, efficient generation of pseudorandom numbers or realization of the Ornstein--Uhlenbeck process.

NestedMP: Enabling cache-aware thread mapping for nested parallel shared memory applications

Abstract It is beneficial to exploit multiple levels of parallelism for a wide range of applications, because a typical server already has tens of processor cores now. As the number of cores in a computer is increasing rapidly, efficient support of nested parallelism will be more and more important. We observe that different task-core mapping schemas may result significant performance difference because modern HPC servers are NUMA multi-core systems. So it is important to control the task-core mapping for nested parallelism. However, the number of threads management mechanism in current parallel programming models, such as OpenMP, does not provide enough information for runtime systems to make optimized decision. As a result, current nested parallel applications often suffer from suboptimal task-core mapping and get significant performance loss. To address this problem, we propose NestedMP, a set of directives which extends OpenMP. NestedMP specifies the number of threads of each nested parallel branch in a declarative way and allows runtime systems to see the whole picture of task trees to make locality-aware task-core mapping. We have implemented NestedMP in GCC 4.8.2 and tested the performance on a 4-way 8-core SandyBridge server. The result shows NestedMP improves the performance significantly over GCC’s OpenMP implementation.

FEAST As A Subspace Iteration Eigensolver Accelerated By Approximate Spectral Projection

The calculation of a segment of eigenvalues and their corresponding eigenvectors of a Hermitian matrix or matrix pencil has many applications. A new density-matrix-based algorithm has been proposed recently and a software package FEAST has been developed. The density-matrix approach allows FEAST's implementation to exploit a key strength of modern computer architectures, namely, multiple levels of parallelism. Consequently, the software package has been well received, especially in the electronic structure community. Nevertheless, theoretical analysis of FEAST has lagged. For instance, the FEAST algorithm has not been proven to converge. This paper offers a detailed numerical analysis of FEAST. In particular, we show that the FEAST algorithm can be understood as an accelerated subspace iteration algorithm in conjunction with the Rayleigh--Ritz procedure. The novelty of FEAST lies in its accelerator, which is a rational matrix function that approximates the spectral projector onto the eigenspace in question. Analysis of the numerical nature of this approximate spectral projector and the resulting subspaces generated in the FEAST algorithm establishes the algorithm's convergence. This paper shows that FEAST is resilient against rounding errors and establishes properties that can be leveraged to enhance the algorithm's robustness. Finally, we propose an extension of FEAST to handle non-Hermitian problems and suggest some future research directions.

PGAS‐FMM: Implementing a distributed fast multipole method using the X10 programming language

SUMMARYThe fast multipole method (FMM) is a complex, multi‐stage algorithm over a distributed tree data structure, with multiple levels of parallelism and inherent data locality. X10 is a modern partitioned global address space language with support for asynchronous activities. The parallel tasks comprising FMM may be expressed in X10 by using a scalable pattern of activities. This paper demonstrates the use of X10 to implement FMM for simulation of electrostatic interactions between ions in a cyclotron resonance mass spectrometer. X10's task‐parallel model is used to express parallelism by using a pattern of activities mapping directly onto the tree. X10's work stealing runtime handles load balancing fine‐grained parallel activities, avoiding the need for explicit work sharing. The use of global references and active messages to create and synchronize parallel activities over a distributed tree structure is also demonstrated. In contrast to previous simulations of ion trajectories in cyclotron resonance mass spectrometers, our code enables both simulation of realistic particle numbers and guaranteed error bounds. Single‐node performance is comparable with the fastest published FMM implementations, and critical expansion operators are faster for high accuracy calculations. A comparison of parallel and sequential codes shows the overhead of activity management and work stealing in this application is low. Scalability is evaluated for 8k cores on a Blue Gene/Q system and 512 cores on a Nehalem/InfiniBand cluster. Copyright © 2013 John Wiley & Sons, Ltd.

Multilevel parallel optimization using massively parallel structural dynamics

A large-scale structural optimization of an electronics package has been completed using a massively parallel structural dynamics code. The optimization goals were to maximize safety margins for stress and acceleration resulting from transient impulse loads, while remaining within strict mass limits. The optimization process utilized nongradient, gradient, and approximate optimization methods in succession to modify shell thickness and foam density values within the electronics package. This combination of optimization methods was successful in improving the performance from an infeasible design that violated response allowables by a factor of two to a completely feasible design with positive design margins, while remaining within the mass limits. In addition, a tradeoff curve of mass versus safety margin was developed to facilitate the design decision process. These studies employed the ASCI Red supercomputer and used multiple levels of parallelism on up to 2560 processors. In total, a series of calculations were performed on ASCI Red in five days, where an equivalent calculation on a single desktop computer would have taken greater than 12 years to complete. This paper conveys the approaches, results, and lessons learnt from this large-scale production design application.

Deep Blue

Deep Blue is the chess machine that defeated then-reigning World Chess Champion Garry Kasparov in a six-game match in 1997. There were a number of factors that contributed to this success, including: • a single-chip chess search engine, • a massively parallel system with multiple levels of parallelism, • a strong emphasis on search extensions, • a complex evaluation function, and • effective use of a Grandmaster game database. This paper describes the Deep Blue system, and gives some of the rationale that went into the design decisions behind Deep Blue.

Parallel changes in large-scale software development

An essential characteristic of large-scale software development is parallel development by teams of developers. How this parallel development is structured and supported has a profound effect on both the quality and timeliness of the product. We conduct an observational case study in which we collect and analyze the change and configuration management history of a legacy system to delineate the boundaries of, and to understand the nature of, the problems encountered in parallel development. The results of our studies are (1) that the degree of parallelism is very highhigher than considered by tool builders; (2) there are multiple levels of parallelism, and the data for some important aspects are uniform and consistent for all levels; (3) the tails of the distributions are long, indicating the tail, rather than the mean, must receive serious attention in providing solutions for these problems; and (4) there is a significant correlation between the degree of parallel work on a given component and the number of quality problems it has. Thus, the results of this study are important both for tool builders and for process and project engineers.

Nested Parallelism: Allocation of Threads to Tasks and OpenMP Implementation

In this paper we discuss the use of nested parallelism. Our claim is that if the problem naturally possesses multiple levels of parallelism, then applying parallelism to all levels may significantly enhance the scalability of your algorithm. This claim is sustained by numerical experiments. We also discuss how to implement multi-level parallelism using OpenMP. We find current OpenMP implementation, based on version 1.0, to have severe limitation for implementing nested parallelization. We then show how this can be circumvented by explicitly assign task to threads. Load balancing issues become more complicated with two (or more) levels of parallelism. To handle this problem, we have designed a distribution algorithm which groups threads into teams, each team being responsible for one course grain outer-level task. This algorithm is proven to produce the optimal load balance, under given assumptions.

The Design of the PROMIS Compiler—Towards Multi-Level Parallelization

Most systems that are under design and likely to be built in the future will employ hierarchical organization with many levels of memory hierarchy and parallelism. In order to efficiently utilize the multiple levels of parallelism available in the target architecture, a parallelizing compiler must orchestrate the interactions of fine-grain and coarse-grain program transformations. This article describes issues of multi-grain parallelization and how they are addressed in the PROMIS compiler design. PROMIS is a multilingual, parallelizing, and retargetable compiler with an integrated frontend and backend operating on a single unified and universal intermediate representation. PROMIS exploits multiple levels of static and dynamic parallelism, ranging from task- and loop-level parallelism to instruction-level parallelism, based on a target architecture description. The frontend and the backend are integrated through a unified internal representation common to the high-level, the low-level, and the instruction-level analyses and transformations.

TOWARDS A DYNAMIC MODEL OF ASSOCIATIVE SEMANTIC MEMORY

When we analyze a particular stimulus, a number of neurons in the brain are specifically activated. The recognition of a visual pattern can be interpreted as the activation of a particular group of such neurons, in a particular way. Some recent results [5] have shown that a group of neurons may respond to a stimulus with a coupled activity. This notion of coupled neural activity can be used to understand the multiple levels of parallelism in the brain. It is known that, in response to a single stimulus, many mental representations are activated in parallel [1]. Our objective is to examine how coupled activity of groups of neurons can explain this parallelism of concept activation in the brain. The neural activity of a single neuron or groups of neurons is simulated. Simple neural networks combining groups of neurons could also be used to simulate the synchronization of neural activities.

Programming probabilistic structural analysis for parallel processing computers

SIGNIFICANT advances have taken place in probabilistic structural analysis (PSA) over the last two decades. Much of this research has focused on basic theory development and the development of approximate analytic solution methods. Practical application of PSA methods has been hampered, however, by their computationally intense nature. Solutions of PSA problems require repeated analyses of structures that are often large and exhibit nonlinear and/or dynamic response behavior. PSA methods, however, are all inherently parallel and ideally suited to implementatio n on parallel processing computers. This synoptic1 summarizes the results of the first phase of research to develop a parallel processing system that can significantly reduce the computational times for large-scale PSA problems. Parallel processing improves the speed with which a computational task is done by breaking it into subtasks and executing as many as possible of these subtasks simultaneously. A summary of the principal ideas in parallel processing and a survey of currently available architecture appears in Sues et al.2 We identify here the multiple levels of parallelism in PSA, describe the development of a parallel stochastic finite element code, and present results of an example application. Although the example application achieved both excellent speedups and greater than 95% efficiency, we conclude that achieving massive parallelism will require overcoming limitations of current parallel architectures. New hardware/software strategies must be developed that keep large numbers of processors busy while minimizing memory requirements and interprocessor communication. Hence, we provide generic hardware and software recommendations for achieving largescale parallel PSA implementation. Contents Parallelism in Probabilistic Structural Mechanics Probabilistic structural mechanics problems are inherently parallel, exhibiting several levels of parallelism. There are two macroscale levels of parallelism: top level parallelism results from parallelism associated with the probabilistic aspects of the problem; and lower level parallelism results from the structural mechanics aspects. There are also many levels of microscale parallelism associated with the structural mechanics aspects of the problem, including both concurrency and vectorization. These sources of parallelism are described in detail in Sues et al. 2