Multiple Input Vectors Research Articles

A Pruning and Feedback Strategy for Locating Reliability-Critical Gates in Combinational Circuits

In nanometric integrated circuits, to harden reliability-critical gates (RCGs) is an important step to improve overall circuit reliability at a low cost. To locate RCGs quickly and efficiently is a key prerequisite for selective hardening at the early stage of circuit design. This article develops a new approach for locating RCGs for multiple input vectors in combinational circuits, using an input vector-oriented pruning technology to identify RCGs, and a sensitivity-based algorithm to measure the criticality of gate reliability (CGR) for each identified RCG. To accelerate the location of RCGs, a feedback-based algorithm mines the accumulated simulation data for each RCG, and a grouping algorithm handles RCGs with similar CGR in the stage of convergence checking. Simulations on 74-series and ISCAS 85 benchmark circuits show that the average accuracy of the proposed method is 0.986 with Monte–Carlo (MC) as the reference and it is 7181 times faster than the MC model. Also, this method performs better than other approximate algorithms in terms of location accuracy and time overhead.

A simpler way to predict flowering and full bloom dates of cherry blossoms by self-organizing maps

Knowledge of flowering and leaf flush phenology is important for a deep understanding of the responses of ecosystem functions, ecosystem services, and biodiversity to climate change. Process-based phenology models, which account statistically for chilling accumulation for endodormancy release and thermal accumulation after endodormancy release, can predict flowering and leaf flush dates, but they are difficult to develop for poorly studied species. A simpler approach is needed. We propose a model of the blooming phenology of Yoshino cherry trees (Cerasus ×yedoensis) based on bidirectional self-organizing maps (SOM). SOM, a data mining approach, is a tool for categorizing patterns in n-dimensional observation data by forming a two-dimensional lattice. The bi-directional SOM was applied to the data of daily mean temperature, using flowering (or full blooming) dates as teacher signals. We inputted daily mean air temperatures during the thermal accumulation period (mainly from February to just before flowering) into multiple input vectors and obtained flowering or full bloom dates into an output vector. The mean absolute errors between predicted and observed dates at 42 locations in Japan ranged from 2.8 to about 4.5 days for flowering and full bloom. The bidirectional SOM approach had a slightly higher error than the process-based phenology model approach, but it has an advantage in predicting flowering and leaf flush dates of poorly studied species under future warming conditions.

Application of ANN and fuzzy logic algorithms for streamflow modelling of Savitri catchment

The streamflow prediction is an essentially important aspect of any watershed modelling. The black box models (soft computing techniques) have proven to be an efficient alternative to physical (traditional) methods for simulating streamflow and sediment yield of the catchments. The present study focusses on development of models using ANN and fuzzy logic (FL) algorithm for predicting the streamflow for catchment of Savitri River Basin. The input vector to these models were daily rainfall, mean daily evaporation, mean daily temperature and lag streamflow used. In the present study, 20 years (1992–2011) rainfall and other hydrological data were considered, of which 13 years (1992–2004) was for training and rest 7 years (2005–2011) for validation of the models. The mode performance was evaluated by R, RMSE, EV, CE, and MAD statistical parameters. It was found that, ANN model performance improved with increasing input vectors. The results with fuzzy logic models predict the streamflow with single input as rainfall better in comparison to multiple input vectors. While comparing both ANN and FL algorithms for prediction of streamflow, ANN model performance is quite superior.

M-IVC: Applying multiple input vectors to co-optimize aging and leakage

With technology scaling, aging effect and leakage pose significant challenge on the reliability of integrated circuits. Existing techniques on co-optimizing circuit aging and leakage either implement in an intrusive way or rely on input vector control (IVC) method. However, intrusive schemes increase the design complexity and induce extra delay and area overheads. IVC method becomes ineffective as the circuit scale increasing. In this paper, a non-intrusive scheme exploiting multiple input vectors (M-IVC) is proposed to co-optimize NBTI-induced degradation and leakage when the circuit steps into standby mode. M-IVC grounds on a new co-optimization model which formulates both the NBTI-induced delay degradation and the average standby leakage as the function of duty cycle. This co-optimization model facilitates to identify a set of optimal duty cycles which result in minimum NBTI-induced degradation and leakage simultaneously. To achieve the optimal duty cycles, an ATPG-like algorithm is proposed to generate multiple input vectors and determine the applying time for each vector. Experimental results demonstrate that with only a small number of vectors, M-IVC can effectively optimize NBTI-induced delay degradation and leakage together and keep the effectiveness as the time of standby period increasing.

A Balanced Capacitive Threshold-Logic Gate

In this paper a new threshold gate is proposed. Its main characteristics are high fan-in (128-inputs), low delay time (8.35 ns), low power consumption (<400 μW) and optimal implementation of any threshold function. The gate can evaluate multiple input vectors in the same evaluation phase with only one clock signal. Synchronous (pipe-line) and asynchronous operations are possible, which makes it very suitable to implement logic designs with reduced depth. HSPICE simulations and simulation with files extracted from a layout in 0.6 μm double-poly CMOS technology are presented, showing the validity of the proposed gate.

The effect of correlation coefficient among multiple input vectors on the efficiency mean in data envelopment analysis

In some of the papers on data envelopment analysis (DEA), there have been explained that if correlation coefficient between each pair of input (output) vectors is strong and positive, one of the input (output) vector could be omitted. The objective of this paper is to determine correlation coefficient threshold that beyond which omission of one or more input vectors have no statistically significant effect on the efficiency mean. The threshold identification in terms of some of the DEA models including CCR, CCRCSW, BCC and BCCCSW are performed. To analyze the data, analysis of variance (ANOVA) is used.

A capacitive threshold-logic gate

A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-of-product and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described.

Two new techniques for unit-delay compiled simulation

The potential change (PC)-set method and the parallel technique for generating compiled unit-delay simulators for acrylic circuits are discussed. The PC-set method analyzes the network, determines the set of potential change times for each net, and generates gate simulations for each potential change. The parallel technique, which is based on the concept of bit-parallel simulation is faster and generates less code than the PC-set method, but it is not amenable to data-parallel simulation of multiple input vectors. Both techniques are based on the well-known levelization algorithm used to generate zero-delay levelized compiled code simulation. Two optimizations of the basic parallel technique are presented, called bit-field trimming and shift elimination. Performance results using the ISCAS 85 benchmarks show a factor-of-four improvement for the PC-set method and a factor-of-ten improvement for the parallel technique. The optimization schemes show an average performance improvement of 47% over the unoptimized simulations. >