Multiple Finite State Machines Research Articles

A memory-efficient deterministic finite automaton-based bit-split string matching scheme using pattern uniqueness in deep packet inspection.

This paper proposes a memory-efficient bit-split string matching scheme for deep packet inspection (DPI). When the number of target patterns becomes large, the memory requirements of the string matching engine become a critical issue. The proposed string matching scheme reduces the memory requirements using the uniqueness of the target patterns in the deterministic finite automaton (DFA)-based bit-split string matching. The pattern grouping extracts a set of unique patterns from the target patterns. In the set of unique patterns, a pattern is not the suffix of any other patterns. Therefore, in the DFA constructed with the set of unique patterns, when only one pattern can be matched in an output state. In the bit-split string matching, multiple finite-state machine (FSM) tiles with several input bit groups are adopted in order to reduce the number of stored state transitions. However, the memory requirements for storing the matching vectors can be large because each bit in the matching vector is used to identify whether its own pattern is matched or not. In our research, the proposed pattern grouping is applied to the multiple FSM tiles in the bit-split string matching. For the set of unique patterns, the memory-based bit-split string matching engine stores only the pattern match index for each state to indicate the match with its own unique pattern. Therefore, the memory requirements are significantly decreased by not storing the matching vectors in the string matchers for the set of unique patterns. The experimental results show that the proposed string matching scheme can reduce the storage cost significantly compared to the previous bit-split string matching methods.

마이크로컨트롤러 인터럽트를 사용한 임베디드시스템의 다중 상태기계 모델링 기반 구현 기법

This paper presents a technique to implement embedded systems using interrupts of the one-chip microcontroller with many peripherals based on a multiple finite state machines model. The multiple finite state machine model utilizes the structure of FSMD used for hardware design and the features of flow control by interrupts. The main finite state machine corresponds to the main program and the sub-state machines corresponds to the interrupt subroutines. Therefore, interrupts from the peripherals can be processed immediately in the sub-state machines. The request and reply variables are used to interface between the finite state machines. Additional operating system is not necessary for the context switching between the main state machine and the sub-state machine, because the flow-control caused by interrupt can be replaced with the switching. An embedded system modeled on multiple finite state machine with ASM charts can be easily implemented by the conversion of ASM charts into C-language programs. This implementation technique can be easily adopted to the hardware oriented embedded systems because of the detail description of the model and the fast response to the interrupt events in the sub-state machine.

A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions

We present a mutation-based validation paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, design error simulation, and model-directed test vector generation. We first present a control-based coverage measure that is aimed at exposing design errors that incorrectly set control signal values. We then describe MVP's high-level concurrent design error simulator that can handle various modeled design errors. We then present fundamental techniques and data structures for analyzing high-level circuit implementations and present various optimizations to speed up the processing of data structures and consequently speed up MVP's overall test generation process. We next introduce a new automatic test vector generation technique for high-level hardware descriptions that generates a test sequence by efficiently solving constraints on multiple finite state machines. To speed up the test generation, MVP is empowered by learning abilities via profiling various aspects of the test generation process. Our experimental results show that MVP's learning abilities and automated test vector generation effectiveness make MVP significantly better than random or pseudorandom validation techniques.

A Parallel “String Matching Engine” for use in High Speed Network Intrusion Detection Systems

This paper describes a finite state machine approach to string matching for an intrusion detection system. To obtain high performance, we typically need to be able to operate on input data that is several bytes wide. However, finite state machine designs become more complex when operating on large input data words, partly because of needing to match the starts and ends of a string that may occur part way through an input data word. Here we use finite state machines that each operate on only a single byte wide data input. We then provide a separate finite state machine for each byte wide data path from a multi-byte wide input data word. By splitting the search strings into multiple interleaved substrings and by combining the outputs from the individual finite state machines in an appropriate way we can perform string matching in parallel across multiple finite state machines. A hardware design for a parallel string matching engine has been generated, built for implementation in a Xilinx Field Programmable Gate Array and tested by simulation. The design is capable of operating at a search rate of 4.7 Gbps with a 32-bit input word size.

Automatic extraction of object-oriented component interfaces

Component-based software design is a popular and effective approach to designing large systems. While components typically have well-defined interfaces, sequencing information---which calls must come in which order---is often not formally specified.This paper proposes using multiple finite statemachine (FSM) submodels to model the interface of a class. A submodel includes a subset of methods that, for example, implement a Java interface, or access some particular field. Each state-modifying method is represented as a state in the FSM, and transitions of the FSMs represent allow able pairs of consecutive methods. In addition, state-preserving methods are constrained to execute only under certain states.We have designed and implemented a system that includes static analyses to deduce illegal call sequences in a program, dynamic instrumentation techniques to extract models from execution runs, and a dynamic model checker that ensures that the code conforms to the model. Extracted models can serve as documentation; they can serve as constraints to be enforced by a static checker; they can be studied directly by developers to determine if the program is exhibiting unexpected behavior; or they can be used to determine the completeness of a test suite.Our system has been run on several large code bases, including the joeq virtual machine, the basic Java libraries, and the Java 2 Enterprise Edition library code. Our experience suggests that this approach yields useful information.

Trellis‐coded multidimensional fast frequency shift keying modulation by use of multistage decoding

The case when the modulation index is 0.5 in continuous phase frequency shift keying (CPFSK) is called fast frequency shift keying (FFSK). In this paper, a trellis-coded multidimensional modulation scheme using FFSK is proposed. In implementing a multidimensional modulation system, the complexity of decoding associated with the maximum likelihood decoding based on a Viterbi algorithm and the trellis coding design become problematic. In particular, the latter is influenced significantly by the path memory of the Viterbi decoder and the size of the scale of the ACS circuit, becoming a big problem in implementing the system. Thus, in this scheme, the complexity of decoding is alleviated by constructing the trellis decoder from multiple finite state machines and using a pseudo-multistage decoding method. Thus, the search and optimization of codes capable of using this multistage decoding algorithm are investigated. The bit error rate performance of codes having less decoding complexity as compared with the past best decoding is evaluated by computer simulation and the efficacy of the proposed scheme is shown. ©1999 Scripta Technica, Electron Comm Jpn Pt 3, 83(3): 70–83, 2000

Trellis-coded multidimensional fast frequency shift keying modulation by use of multistage decoding

The case when the modulation index is 0.5 in continuous phase frequency shift keying (CPFSK) is called fast frequency shift keying (FFSK). In this paper, a trellis-coded multidimensional modulation scheme using FFSK is proposed. In implementing a multidimensional modulation system, the complexity of decoding associated with the maximum likelihood decoding based on a Viterbi algorithm and the trellis coding design become problematic. In particular, the latter is influenced significantly by the path memory of the Viterbi decoder and the size of the scale of the ACS circuit, becoming a big problem in implementing the system. Thus, in this scheme, the complexity of decoding is alleviated by constructing the trellis decoder from multiple finite state machines and using a pseudo-multistage decoding method. Thus, the search and optimization of codes capable of using this multistage decoding algorithm are investigated. The bit error rate performance of codes having less decoding complexity as compared with the past best decoding is evaluated by computer simulation and the efficacy of the proposed scheme is shown. ©1999 Scripta Technica, Electron Comm Jpn Pt 3, 83(3): 70–83, 2000

Control unit synthesis from a high-level language

Control Unit Synthesizer (CUS) is a language and a synthesizer for generating VLSI layouts of control units from a user's functional specification. CUS synthesizes multiple finite state machines (FSMs), which are organized hierarchically and interconnected by global variables and a FORK/JOIN protocol. High-level constructs like WHILE loops. FOR loops, registered and nonregistered variables, arbitrarily complex Boolean expressions, and nested statements allow the user to write descriptions of FSMs in a natural manner. The generated circuit is simulated at the logic-level using symbolic names. The resulting layout size is similar or better than manual layout.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>