Multiple Digital Signal Processors Research Articles

Real-Time Simulation System for Small Scale Regional Integrated Energy Systems

Regional Integrated Energy Systems (RIESs) integrate wide spectrum of energy sources and storage with optimized energy management and further pollution reduction. This paper presents a real-time simulation system for RIESs powered by multiple digital signal processors (DSPs) with different means of data exchange. The RIES encompasses the DC microgrid (DMG), the district heat network (DHN), and the natural gas network (NGN). To realize multi-energy flow simulation, averaged switch models are investigated for different types of device-level units in the DMG, and the unified energy path method is used to build circuit-dual models of the DHN and NGN. A hierarchical island strategy (HIS) and a multi-energy dispatch strategy (MEDS) are proposed to enhance the energy flow control and operating efficiency. The two-layer HIS can adjust the operating status of device-level units in real time to achieve bus voltage stability in the DMG; MEDS uses energy conversion devices to decouple multi-energy flows and adopts the decomposed flow method to calculate the flow results for each network. The real-time simulation hardware platform is built, and both electricity-led and thermal-led experiments are carried out to verify the accuracy of models and the effectiveness of the proposed strategy. The proposed system with an energy management strategy aims to provide substantial theoretical and practical contributions to the control and simulation of RIESs, thus supporting the advancement of integrated energy systems.

An intelligent BIM-enabled digital twin framework for real-time structural health monitoring using wireless IoT sensing, digital signal processing, and structural analysis

Structural health monitoring (SHM) of civil infrastructure is critically important due to its direct influence on public safety and economic activities. Exiting Building Information Modeling (BIM)-based SHM systems often use offline data processing techniques to analyze and visualize structural health data. Despite some of them adopting Internet of Things (IoT) to enable real-time sensor data collection, sensor data quality still remains uncertain due to a lack of sensor signal preprocessing in those existing systems. Additionally, the IoT-based SHM systems often disregard structural analysis domain knowledge, which is important for accurate and precise SHM. Therefore, there is still a need to improve existing systems and practices by enabling more efficient and reliable data collection and processing as well as providing more representative SHM data visualization in BIM. As such, this paper proposes an intelligent BIM-enabled digital twin (DT) framework that integrates wireless IoT sensing and communication, digital signal processing (DSP), and structural analysis domain knowledge. The proposed system (1) leverages IoT sensing and wireless communication to enable autonomous and real-time SHM sensor data collection and transmission, (2) applies and compares multiple DSP techniques to preprocess the sensor data/signals, and (3) innovatively embraces structural analysis expertise into structural behavior visualization in BIM by performing sensor data interpolation for enabling the visualization of structural behaviors at different locations of a structural element/component. The proposed BIM-enabled DT framework was demonstrated and tested for monitoring and visualizing the structural deformations of critical structural components using a prototyped structural frame subject to bending forces. The developed framework could be used and extended for any structural elements (such as beams, columns, trusses, slabs, arches, bracings, walls, footings, foundations, and girders, among others) and could be applied to any kind of structure. Experimental results showed that the proposed framework could effectively monitor and intuitively visualize the structural deformations under different load configurations with a high DT updating frequency of 5 Hz. The innovation of this study is reflected by integrating structural analysis expertise with IoT-enabling sensing data analytics in order to improve the representativeness of real-time structural behavior visualization in BIM and to advance the DT-based SHM systems in a faster and more adaptive direction. Ultimately, this paper contributes to the body of knowledge by developing a generic and easily extendable BIM-enabled DT framework for SHM with high sensor data quality and improved visualization to advance the existing practices of BIM-based SHM for civil infrastructure asset management.

Demonstration of using two aperture pairs combined with multiple-mode receivers and MIMO signal processing for enhanced tolerance to turbulence and misalignment in a 10 Gbit/s QPSK FSO link

We utilize aperture diversity combined with multiple-mode receivers and multiple-input-multiple-output (MIMO) digital signal processing (DSP) to demonstrate enhanced tolerance to atmospheric turbulence and spatial misalignment in a 10 Gbit/s quadrature-phase-shift-keyed (QPSK) free-space optical (FSO) link. Turbulence and misalignment could cause power coupling from the fundamental Gaussian mode into higher-order modes. Therefore, we detect power from multiple modes and use MIMO DSP to enhance the recovery of the original data. In our approach, (a) each of multiple transmitter apertures transmits a single fundamental Gaussian beam carrying the same data stream, (b) each of multiple receiver apertures detects the signals that are coupled from the fundamental Gaussian beams to multiple orbital angular momentum (OAM) modes, and (c) MIMO DSP is used to recover the data over multiple modes and receivers. Our simulation shows that the outage probability could be reduced from >0.1 to <0.01. Moreover, we experimentally demonstrate the scheme by transmitting two fundamental Gaussian beams carrying the same data stream and recovering the signals on OAM modes 0 and +1 at each receiver aperture. We measure an up to ∼10dB power-penalty reduction for a bit error rate (BER) at the 7% forward error correction limit for a 10 Gbit/s QPSK signal.

Design and Development of a Real-Time Multi-DSPs and FPGA-Based DPOS for InSAR Applications

With the development of the novel remote sensing system such as array antenna interference synthetic aperture radar (InSAR), it is in urgent demand to design and develop an airborne distributed position and orientation system (DPOS) to provide multi-node time-spatial reference information accurately. To solve the problem, this paper describes a novel design and fabrication of DPOS, which integrates the main strapdown inertial navigation system (SINS), global position satellite (GPS), multiple slave inertial measurement units (IMUs), and distributed navigation processing computer system. In the proposed system, multiple digital signal processors (multi-DSPs) are used for multiple inertial navigation solutions and Kalman filter computations, and a field programmable gate array is used for creating an efficient interface of the GPS and multiple IMUs with the multi-DSPs. This also helps reduce the count of the total chips, resulting in a compact system. The system is designed to provide synchronous multi-node real-time high-precision navigation solutions with an update of 200 Hz. In order to verify the performance of DPOS, the real flight test, which combined InSAR and DPOS, was conducted and showed the proposed system can help compensate the motion error of the high-resolution interference mapping more efficiently than the single POS.

Real-Time Programmable DSPs for Video Processing: The Challenges of Their Development

Video signals can be processed by homogeneous multiple digital signal processors (DSPs) using the overlap-save method. The target application of the video signal processor (VSP) was video phones and video conferencing, along with the development of International Telecommunication Union-Telecommunication Standardization Sector (ITU-T) Recommendation H.261, video transmission over ISDN lines on which data rates are multiples of 64 kb/s. A commercial H.261 codec was developed based on the proposed VSP architecture, and the extension to high-definition TV (HDTV) signal processing had also been achieved and demonstrated. This article describes the challenge of real-time programmable VSP development during the 1980s.

ULA-OP 256: A 256-Channel Open Scanner for Development and Real-Time Implementation of New Ultrasound Methods.

Open scanners offer an increasing support to the ultrasound researchers who are involved in the experimental test of novel methods. Each system presents specific performance in terms of number of channels, flexibility, processing power, data storage capability, and overall dimensions. This paper reports the design criteria and hardware/software implementation details of a new 256-channel ultrasound advanced open platform. This system is organized in a modular architecture, including multiple front-end boards, interconnected by a high-speed (80 Gb/s) ring, capable of finely controlling all transmit (TX) and receive (RX) signals. High flexibility and processing power (equivalent to 2500 GFLOP) are guaranteed by the possibility of individually programming multiple digital signal processors and field programmable gate arrays. Eighty GB of on-board memory are available for the storage of prebeamforming, postbeamforming, and baseband data. The use of latest generation devices allowed to integrate all needed electronics in a small size ( 34 cm ×30 cm ×26 cm). The system implements a multiline beamformer that allows obtaining images of 96 lines by 2048 depths at a frame rate of 720 Hz (expandable to 3000 Hz). The multiline beamforming capability is also exploited to implement a real-time vector Doppler scheme in which a single TX and two independent RX apertures are simultaneously used to maintain the analysis over a full pulse repetition frequency range.

3차원 탐색 레이더용 고속 실시간 신호처리기 개발

A 3-D surveillance radar is a pulsed-doppler radar to provide various target information, such as range, doppler and angle by performing TWS. This paper introduces HW/SW architecture of radar signal processing board to process in real-time using high-speed multiple DSP(Digital Signal Processor) based on COTS. Moreover, we introduced a implemented algorithm consisted of clutter map creation/renewal, FIR(Finite Impulse Response) filter for rejection of zero velocity components, doppler filter, hybrid CFAR and finally presented computational burden of each algorithm by performing operational test using a beacon.

Multi-DSP and -FPGA-Based Fully Digital Control System for Cascaded Multilevel Converters Used in FACTS Applications

In this paper, a fully digital controller based on multiple digital signal processor (DSP) and field-programmable gate array (FPGA) boards has been proposed for parallel-operated cascaded multilevel converters (CMC) used in flexible AC transmission system (FACTS) applications. The proposed system is composed of a DSP-based master controller in combination with a multiple number of slave DSP boards, FPGA boards, microcontrollers, a programmable logic controller (PLC), an industrial computer, and their peripherals in interaction. Intercommunication of these digital controllers is achieved mainly through fiber-optic links, via synchronous serial data link wherever a high-speed, full duplex communication is needed, and via asynchronous serial communication interface wherever relatively slow communication speed is required. The proposed fully-digital control system has been implemented on a sample 11-level CMC-based 154-kV, <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$+/-$</tex></formula> 50-MVAr transmission type static synchronous compensator (T-STATCOM). Field test results have shown that the proposed fully digital control system provides good transient response and steady-state characteristics for the oveall system including protection and monitoring functions.

A Multiprocessor Simulation for Advanced Signal Processing Applications

This paper presents a multiprocessor simulation that executes an advanced signal processing algorithm i.e. beamforming for sensor arrays. The simulation model involves several desktop PCs. It demonstrates how an advanced signal processing technique can be implemented on a system that is based on multiple digital signal processors (DSPs) in the absence of actual hardware. It uses MATLAB, a DSP simulator, and an open source MATLAB based message passing interface (MPI). The simulation applies a frequency-domain beamformer to a linear sensor array and the results show efficient utilization of processors for real-time operation.

A real-time control system for single-phase unified power flow controllers

This paper proposes a real-time control system for a single-phase unified power flow controller (UPFC) which is constructed as a pilot power-quality compensation equipment of an electrical railway, and shows simulation and experimental results. For simulation, the control system is modeled in the form of block diagrams by using the Simulink, where the main control effort is focused on the power flow control with the UPFC and the hysteresis current controller is adopted to control the single-phase inverters of the UPFC. And for a small-scale rapid prototyping of the UPFC-equipped control system, the simulation blocks are modified and a real-time control platform is developed by using the real-time workshop and multiple digital signal processors. Both simulation and experiment results have proved the effectiveness of the proposed control system.

Parallel Ray Tracing Using the Message Passing Interface

Ray-tracing software is available for lens design and for general optical systems modeling. It tends to be designed to run on a single processor and can be very time consuming if the number of rays traced is large. Previously, multiple digital signal processors (DSPs) have been used to perform such simulations. This approach is attractive because DSPs are inexpensive, and the time saved through parallel processing can be significant. In this paper, we report a nearly linear relationship between the number of processors, and the rate of ray tracing with as many as 839 processors operating in parallel on the Naval Research Laboratory's Cray XD-1 computer with the Message Passing Interface (MPI). In going from 1 to 839 processors, we achieved an efficiency of 97.9% and a normalized ray-tracing rate of in a system with 22 planar surfaces, two paraboloid reflectors, and one hyperboloid refractor. The need for a load-balancing software was obviated by the use of a prime number of processors.

A 3-D Baseband Signal Analyzer Prototype for 3G Mobile Telecommunication Systems

The paper deals with the realization of a new instrument for the qualification of third-generation (3G) mobile telecommunication systems. It is based on the parallel computing of a time-frequency representation called smoothed pseudo-Wigner-Ville distribution (SPWVD) on a multiple digital signal processor architecture. The SPWVD allows the performance of signal analysis simultaneously in both the time and frequency domain. The hardware and software implementations of the instrument prototype are presented and discussed. Then, the first validation results, obtained on wide-band code-division-multiplexing access (W-CDMA) signals compliant with the 3rd Generation Partnership Program (3GPP) standard, are reported.

Optical Ray Tracing Using Parallel Processors

One of the instruments on the sun-synchronous Terra (EOS AM) and Aqua (EOS PM) spacecraft, the Moderate Resolution Spectroradiometer (MODIS), obtains calibration data once during every orbit. Observations of the sun permit corrections to observations of the Earth during the ensuing orbit. Although the instrument was designed to receive uniform sunlight over the entire surface of its detector, the sunlight was in fact not uniform. While this did not adversely affect the calibration, it nonetheless implied a lack of understanding of how the optical system really functioned. To learn what was wrong, NASA used an optical ray-tracing program on a DEC Alpha computer. The results correlated well with the observations made by the instrument itself, but it took nearly two weeks to complete the computer simulation, a discouragingly long time. This paper describes the algorithm and its implementation in a system with multiple digital signal processor (DSP) chips operating in parallel. Timing data show a highly linear relationship between the number of DSPs present and the speed of the computation. Administrative overhead is negligible compared to the time taken to compute ray trajectories. This implies that many more than just four DSPs could be harnessed before administrative overhead would begin to be significant.

A high-performance communication service for parallel computing on distributed DSP systems

Rapid increases in the complexity of algorithms for real-time signal processing applications have led to performance requirements exceeding the capabilities of conventional digital signal processor (DSP) architectures. Many applications, such as autonomous sonar arrays, are distributed in nature and amenable to parallel computing on embedded systems constructed from multiple DSPs networked together. However, to realize the full potential of such applications, a lightweight service for message-passing communication and parallel process coordination is needed that is able to provide high throughput and low latency while minimizing processor and memory utilization. This paper presents the design and analysis of such a service, based on the message passing interface specification, for unicast and collective communications.

A multi-DSP based instrument on a VXI C-size module for real-time measurements

In this paper, the design and implementation of a high-performance measuring instrument based on multiple digital signal processors is discussed. This system can embody a number of special signal processing and analog I/O modules, specifically designed to obtain the flexibility and scalability to meet the needs of real-time measurement applications. It has been mounted on a prototyping card and interfaced with the VXIbus backplane. Some issues related to the hardware and software design are discussed. A first application, namely the on-line spectral measurement of two input signals, e.g., voltage and current in a power circuit is discussed, reporting the first experimental results.

A real-time encoding and decoding system for nonlinear HDTV editor

A real-time encoding and decoding system (REDS) for HDTV that can be used for nonlinear HDTV editing in studio has been developed. The intrapicture coding of motion JPEG is implemented and optimized in the REDS so that a high-quality image can be recovered for the nonlinear editing. The REDS has a parallel architecture with multiple programmable digital signal processors (DSP) and reconfigurable field programmable logic devices (FPLD). The HDTV image is spatially partitioned and concurrently processed by the multiple processors. The programmable DSPs perform the discrete cosine transform and quantization to reduce the spatial redundancy of the HDTV image, whereas the FPLDs perform the variable length coding to reduce the statistical redundancy. In addition, field-based quantization matrices are developed for HDTV images. The REDS has the programmability and the random accessibility of image frames, the two most important features for a nonlinear HDTV editing system. © 2000 John Wiley & Sons, Inc. Int J Imaging Syst Technol 11, 152–157, 2000

Real-time emulation for power equipment development. Part 1: Real-time simulation

Simulation is becoming increasingly useful in the design of complex systems. Offline simulation is commonplace but there are many issues which can only be examined if the system is simulated at its true speed. A typical example is the interaction between clocked digital systems and continuous processes. The paper reports results from a real-time simulator for an inverter-supplied induction motor drive. The simulator is formed using multiple digital signal processors with task separation to allow real-time modelling down to detailed power device switching level. The system allows the drive controller to be realistically tested in the real-time simulation environment. The system has been shown to be in good agreement with an actual drive running in parallel with the simulator. The paper examines the limits imposed by practical hardware on the level of simulation that is possible.

Simulation of multi-microphone hearing aids in multiple interference environments.

In this study, the advantages of Digital Signal Processing (DSP) hardware for hearing aids are investigated in the context of multiple microphone arrays. One key question in multiple microphone DSP system design remains the allocation of processing resources between the number of microphones and the number of adjustable tap weights applied to each microphone. This study addresses the appropriate distribution of these resources for currently implementable adaptive DSP systems. Comparisons are made by computer simulation that includes acoustic headshadow, reverberation effects and non-ideal microphone array hardware in a wide variety of environments. Variations in the number of interfering sources, the amount of reverberation and the microphone array configuration leads to several important conclusions. Performance improvements provided by the processors are reported as the broadband unweighted signal-to-babble ratio of pre-emphasized speech and speech-shaped babble. Results are demonstrated for both fixed and robust adaptive systems.

Rapid prototyping on the Georgia Tech digital signal multiprocessor

Signal processing supercomputers consisting of multiple programmable digital signal processors offer impressive computational performance while retaining flexibility of programming. The single most important factor limiting their performance has been the lack of a sophisticated software compiling and scheduling environment. Three generations of digital signal multiprocessors (DSMPs) have been designed at the DSP Laboratory at Georgia Tech in the past decade. The authors develop and discuss the schedulers developed for the Georgia Tech DSMP (I-III), and present new techniques that combine a high level description of DSPs together with a theoretical analysis of the performance bounds on synchronous multiprocessors to deliver a significant improvement in the efficiency of prototyping. The DSMP-C1 prototyping environment is presented in some detail, and its superior performance on digital signal processing applications relative to conventional schedulers is demonstrated. >

Selection criteria in the development of a multiple processor based DSP system

This paper notes the selection criteria and the hardware/software alternatives for the construction of a multiple processor system dedicated to handling digital signal processing (DSP) applications, primarily for the analysis of speech signals. The paper initially presents brief descriptions of the different architectural options available for a multiple DSP system. A list of the criteria to be used in the selection of the type of DSP system is detailed and the criteria are then used to aid in the selection of the architecture. From the criteria it is concluded that the use of a loosely coupled transputer based system allows the maximum flexibility for such a system. To aid in the real-time operation of the system it is further proposed to incorporate a front-end data processing mechanism based on the combination of a transputer and a floating-point DSP processor.