Multiple Delayed Signal Cancellation Research Articles

Multiple Delayed Signal Cancellation Filter-Based Enhanced Frequency-Locked Loop Under Adverse Grid Conditions

An accurate and prompt estimation of phase angles, frequency, and magnitudes of the grid voltage is extremely important in paving a good platform for a fast and reliable operation of power grid monitoring, protection, and control. The phase-locked loop (PLL) served this purpose for decades, while the concept of the frequency-locked loop (FLL) has been proposed more recently. Even though the FLL and the PLL share some similarities, some differences still exist. Further research on FLLs can boost their capabilities and open up new windows in designing devices for grid synchronization. Multiple delayed signal cancellation (MDSC) filters are a peculiar system of filters. Their applications to FLLs can enrich FLL’s performance. This article focuses on applying the stationary reference frame MDSC filters at in-loop and prefiltering stages of the FLL and compares its effectiveness with widely used cascaded delayed signal cancellation (CDSC) and complex bandpass filter (CBF) based filtering techniques. The application of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$K$</tex-math></inline-formula> -factor-methodology-based controller design to FLLs has also been explored for dynamic performance enhancements. A new cascaded multiple delayed signal cancellation (CMDSC) filter is proposed and is compared with its CDSC counterpart proposed in the literature to address the effects of dc offsets and imbalances under adverse grid conditions. The effectiveness of the proposed method is verified through OPAL-RT real-time simulations and dSPACE ds1104 and TMS320F28335 microcontroller experimental test bench.

Multiple Delayed Signal Cancellation PLL Based Unit Vector Template PWM Controller for ZSI-DVR Operation Under Adverse Conditions

Multiple Delayed Signal Cancellation PLL Based Unit Vector Template PWM Controller for ZSI-DVR Operation Under Adverse Conditions

Multiple Delayed Signal Cancellation PLL Based Unit Vector Template PWM Controller for ZSI-DVR Operation Under Adverse Conditions

Multiple Delayed Signal Cancellation PLL Based Unit Vector Template PWM Controller for ZSI-DVR Operation Under Adverse Conditions

Control of transformerless T-type DVR using multiple delayed signal cancellation PLL under unbalanced and distorted grid condition

In the near future, the power system network may experience severe voltage distortions due to association of renewable energy sources (RES), and the large penetration of power electronic based loads into the microgrid. To protect sensitive loads from these distorted and unbalanced grid conditions, the commonly used dynamic voltage restorer (DVR) requires effective control algorithms. The effective control algorithm comprises a controller, and accurate estimation of grid phase angle/frequency, and magnitude, thereby the reference DVR voltage is accurately estimated. The synchronous reference frame based phased locked loop (SRF-PLL) is commonly used for phase angle estimation. However, during unbalanced, distorted, and dc-offset conditions, the performance of SRF-PLL is unsatisfactory. To improve its performance, it is cascaded with prefilters such as dual second order generalized integrator (DSOGI), cascaded delayed signal cancellation (CDSC), and multiple delayed signal cancellation (MDSC). Among these prefilters, MDSC has superior performance under all grid conditions with less delay time and memory requirement. In addition to an effective control algorithm, the DVR system requires high power density converters. The power density of the system is increased using transformerless T-type converter. In this paper, the effectiveness of MDSC-PLL for the transformerless T-type converter based DVR is evaluated in MATLAB/Simulink for various grid conditions such as voltage sag/swell, unbalance voltage sag/swell, harmonics, and dc-offset.

Single-Phase Enhanced Phase-Locked Loops Based on Multiple Delayed Signal Cancellation Filters for Micro-Grid Applications

The grid voltage information such as the phase-angle, the frequency, and the amplitude is crucial for the design of synchronization and control of power converters in the micro-grid. The conventional approach to estimate the grid voltage information is accomplished by phase-locked loop (PLL) techniques. Among various existing PLL techniques, filter-based PLLs can provide more accurate estimations even under adverse grid conditions. In this paper, a new single-phase filtering technique based on multiple delayed signal cancellation (MDSC) is proposed for extracting both in-phase and quadrature components of the selected harmonic order of the single-phase grid voltage signal. This MDSC technique can be realized in both the direct-form and the recursive-form. In comparison with existing single-phase cascaded delayed signal cancellation (CDSC) techniques, this MDSC technique utilizes less memory for the extraction of grid voltage fundamental frequency component. The proposed MDSC filter can be applied as a pre-filter to the enhanced PLL (EPLL) for the prompt and accurate estimations of the grid voltage information under adverse grid conditions. Both frequency adaptive and non-adaptive MDSC-based EPLL schemes are proposed in this paper. To validate the effectiveness of the proposed methods, experiments are conducted on the MDSC-based EPLLs and compared with the CDSC-EPLL under various grid voltage disturbances.

Dynamic Performance Enhancement of Single-Phase and Two-Phase Enhanced Phase-Locked Loops by Using In-Loop Multiple Delayed Signal Cancellation Filters

The estimation of phase-angle, frequency, and amplitude are vital for the control of grid-connected power electronic systems in both single-phase and three-phase systems. The single-phase enhanced phase-locked loop (1P-EPLL) and two-phase enhanced phase-locked loop (2P-EPLL) techniques can be used to estimate single-phase and three-phase grid voltage quantities, respectively. However, under the presence of harmonics, unbalance, and dc offsets, the estimated quantities by these enhanced phase-locked loops (EPLLs) may contain periodic ripples. These periodic ripples are eliminated by using multiple delayed signal cancellation (MDSC) filters in the phase-angle estimation loop and amplitude estimation loop of these EPLLs. To improve the dynamic responses of MDSC-based EPLLs, proportional-integral (PI) controller is replaced with a proportional-integral-derivative (PID) controller. The design guidelines for choosing the control parameters are provided. The MDSC filters in the EPLLs are realized both in direct-form and recursive-form structures. The proposed EPLLs are verified experimentally by using real-time system and compared with recent advanced EPLLs.

Recursive Implementation of Multiple Delayed Signal Cancellation Operators and Their Applications in Prefiltered and In-Loop Filtered PLLs Under Adverse Grid Conditions

Phase-locked loops (PLLs) are widely utilized for grid synchronization and control of power electronic converters. More recently, both in-loop-filtered- and prefiltered-based PLLs have become more popular due to their prompt and accurate estimations of grid voltage quantities. In the past, an advanced filter viz., multiple delayed signal cancellation (MDSC) operators, has been successfully investigated in both $\alpha \beta$ -frame and $dq$ -frame for extracting fundamental-frequency positive-sequence grid voltage quantities by using conventional synchronous reference frame PLL. These operators can provide more flexibility to configure the delay time and undesired harmonics in comparison with the existing cascaded delayed signal cancellation operators. In this paper, the recursive-form structures of MDSC operators are analyzed, which are derived from the direct-form MDSC realizations. The recursive-form structures of MDSC operators are simple in implementation when compared to direct-form realizations. With the recursive-form MDSC implementations, both prefiltered MDSC-PLL and in-loop filtered MDSC-PLL will be investigated in detail. The design guidelines of these recursive-form-based MDSC-PLLs are presented. Comparison studies of the proposed PLLs and the validation of their dynamic performances are done by experimental verifications.

Three-Phase PLLs by Using Frequency Adaptive Multiple Delayed Signal Cancellation Prefilters Under Adverse Grid Conditions

Phase-locked loops (PLLs) are the most widely adopted techniques for synchronization of distributed generation units to the utility grid. However, when the grid voltage is polluted with severe unbalances and harmonics, the accuracy and performance of the conventional PLL will be deteriorated. This paper proposes a novel filtering technique, called the multiple delayed signal cancellation (MDSC), for improving the dynamic performance of the conventional synchronous reference frame (SRF)-PLL under adverse three-phase grid conditions. Theoretical developments of $dq$ -frame and $\alpha \beta$ -frame MDSC operators are investigated. The analysis shows that these MDSC operators can provide more flexibility to configure the lowest undesired harmonics. Since the MDSC operators possess multiple delayed signals in parallel, the delay time introduced by the operators can be reduced by selecting a suitable number of transfer delays. Therefore, the MDSC operators can be configured to have less delay time in comparison with the cascaded delayed signal cancellation operators with the same harmonic elimination capability. These two MDSC operators are utilized as a prefiltering stage to the conventional SRF-PLL to improve the dynamic responses. Since MDSC operators are dependent on grid frequency excursions, a new frequency adaptation scheme for the MDSC operators is also proposed for providing fast grid frequency estimations in designing the MDSC prefilter based PLLs. Experimental verifications demonstrate the effectiveness of the proposed PLLs and provide good dynamic responses when compared with the recent advanced PLLs.

Multiple DSC Filter-Based Three-Phase EPLL for Nonideal Grid Synchronization

This paper originally analyzes the effect of the harmonics, dc offsets, and unbalance on the three-phase enhanced phase-locked loop (3P-EPLL). It proves that 3P-EPLL is not able to accurately estimate the amplitude, phase angle, and frequency of the grid in such cases. In order to correctly estimate the grid synchronous information even under the nonideal grid conditions, an improved 3P-EPLL combined with the multiple delayed signal cancellation (DSC) filters is proposed. A DSC operator is set at the each input of 3P-EPLL to eliminate the input dc offsets and even-order harmonics. And the cascaded DSC (CDSC) module is plugged in both the frequency and amplitude loops to remove the effect of most of the odd-order harmonics and unbalance. The relationship between the delay constant of the DSC operator and the order of the harmonics hoping to eliminate is derived to design the structure of the CDSC module and determine the delay constant of each DSC operator in the CDSC module. Detailed experimental results of the standard 3P-EPLL and proposed one validate the theoretical analysis and the proposed phase-locked loop.