Multiple Data Paths Research Articles

Design of a Classification Recognition Model for Bone and Muscle Anatomical Imaging Based on Convolutional Neural Network and 3D Magnetic Resonance.

In this paper, we use convolutional neural networks to conduct in-depth research and analysis on the classification and recognition of bone and muscle anatomical imaging graphics of 3D magnetic resonance and design corresponding models for practical applications. A series of medical image segmentation models based on convolutional neural networks is proposed. In this paper, firstly, a separated attention mechanism is introduced in the model, which divides the input data into multiple paths, applies self-attention weights to adjacent data paths, and finally fuses the weighted values to form the basic convolutional block. This structure has multiple parallel data paths, which increases the width of the network and therefore improves the feature extraction capability of the model. Then, this paper proposes a bidirectional feature pyramid for medical image segmentation task, which has top-down and bottom-up data paths, and, together with jump connections, can fully interact with feature maps at different scales. After that, a new activation function Mish is introduced, and its advantages over other activation functions are experimentally demonstrated. Finally, for the situation that medical image annotations are not easy to obtain, a semisupervised learning method is introduced in the model training process, and the effectiveness of this method is experimentally demonstrated. The joint network first denoises the input image, then super-resolution mapping is performed on the noise-removed feature map, and finally, the super-resolution 3D-MR image is obtained. We update the network by combining the denoising loss and super-resolution loss during the joint network training process. The experimental results show that the joint network with denoising first and then super-resolution outperforms the joint network with other task order and outperforms the method that performs the two tasks separately and the proposed method in this paper has the optimal performance.

Networked Delay Control for 5G Wireless Machine-Type Communications Using Multiconnectivity

Automatic control using ultrareliable and low latency communication is one of the potential applications of the new fifth-generation wireless systems. A remaining challenge is then to guarantee a low end-to-end delay with low jitter over combined internet and wireless interfaces that are packet switched and capacity optimized. The main novelty of this paper is to introduce stringent delay control to meet this challenge, over simultaneous multiple data paths. The proposed multiple-input-multiple-output (MIMO) cascade control system is nonlinear since the dwell times of the transmission node queues used as actuators cannot be negative. Stability analysis based on integral quadratic constraint theory is, therefore, applied to characterize the global stability of the controller. The practical performance is evaluated with experiments using product like test bed C++ code. It is stressed that the proposed controller does not require internode time synchronization.

Efficient and Reliable Application Layer Multicast for Flash Dissemination

To disseminate messages from a single source to a large number of targeted receivers, a natural approach is the tree-based application layer multicast (ALM). In time-constrained flash dissemination scenarios, e.g. earthquake early warning, where time is of the essence, the reliable extensions of the tree-based ALM using ack-based failure recovery protocols cannot support reliable dissemination in the timeframe needed. In this paper, we propose FaReCast which exploits path diversity, i.e., exploit the use of multiple data paths, to achieve fast and reliable data dissemination. First, we design a forest-based M2M (Multiple parents-To-Multiple children) ALM structure where every node has multiple children and multiple parents. The intuition is to enable lower dissemination latency through multiple children, while enabling higher reliability through multiple parents. In order to maintain the M2M ALM structure in a scalable and reliable manner, we develop a DHT-based Distributed Configuration Manager. Second, we design multidirectional multicasting algorithms that effectively utilize the multiple data paths in the M2M ALM structure. A key aspect of our reliable dissemination mechanism is that nodes, in addition to communicating the data to children, also selectively disseminate the data to parents and siblings. As compared to trees using traditional multicasting algorithm, we observe an 80 percent improvement in reliability under 20 percent of failed nodes with no significant increase in latency for over 99 percent of the nodes. Moreover, we notice that FaReCast can reduce the network overhead more than 50 percent by tuning the M2M structure, as compared to the other reliable ALM based disseminations.

A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications

This brief presents a fast Fourier transform (FFT) processor that provides high throughput rate (T.R.) by applying the eight-data-path pipelined approach for wireless personal area network applications. The hardware costs, including the power consumption and area, increase due to multiple data paths and increased wordlength along stages. To resolve these issues, a novel simplification method to reduce the hardware cost in multiplication units of the multiple-path FFT approach is proposed. A multidata scaling scheme to reduce wordlengths while preserving the signal-to-quantization-noise ratio is also presented. Using UMC 90-nm 1P9M technology, a 2048-point FFT processor test chip has been designed, and its 128-point FFT kernel has been fabricated for ultrawideband (UWB) applications and also for verification. The 2048-point FFT processor can provide a T.R. of 2.4 GS/s at 300 MHz with a power consumption of 159 mW. Compared with the four-data-path approach, a power consumption saving of about 30% can be achieved under the same T.R. In addition, the 128-point FFT kernel test chip has a measured power consumption of 6.8 mW with a T.R. of 409.6 MS/s at 52 MHz to meet the UWB standard with a saving in power consumption of about 40%.

A Scalable Priority-Based Multi-Path Routing Protocol for Wireless Sensor Networks

In this paper, a scalable priority-based multi-path routing protocol (PRIMP) is proposed for wireless sensor networks to offer extended network lifetime and robust network fault tolerance, under the context of stringent energy constraint and vulnerability of sensors to dynamic environmental conditions. A novel interest dissemination strategy which invokes an on-demand virtual source technique is designed in PRIMP to minimize communication overheads and energy wastage. In routing, data traffic is distributed over multiple braided data paths simultaneously by a priority-based probabilistic approach at each hop to achieve the robustness against the unreliable transmission due to frequent node failures. Extensive simulations validate that PRIMP exhibits significantly better performance in energy conservation, load-balancing and data delivery than comparable schemes, while at the same time PRIMP achieves a nice scalability feature in terms of energy dissipation with various network sizes and network densities. Last but not least, PRIMP addresses the slow startup problem that is prevalent in data-centric routing schemes.

Evaluation of hardware and software schedulers for embedded switches

High-speed packet switches become increasingly important to embedded systems because they provide multiple parallel data paths necessary in emerging systems such as embedded multiprocessors, multiprotocol communication processors, and so on. The most promising architecture for embedded switches is the one that uses multiple input queues, due to its low-cost integration in conventional embedded systems, which include memory management subsystems. Such switches require high-speed schedulers, in order to resolve conflicts among packet destinations and to achieve low latency, high bandwidth communication, while providing fairness guarantees. In general, these schedulers are categorized as centralized or distributed, depending on their operation. In this paper, we evaluate hardware and software implementations of two schedulers: 2-dimensional round-robin and FIRM, which are centralized and distributed, respectively. The evaluation is performed for embedded system implementation, on a system that includes an FPGA and an embedded processor on-chip. The performance results show that, in contrast to expectations, centralized schedulers provide better performance than distributed ones in hardware implementations. In software implementations for embedded processors, surprisingly, distributed schedulers achieve better performance, due to better management of the processor's limited resources and simpler code; our experiments have shown that compilers for embedded systems are quite limited and require significant improvement. Finally, we evaluate the scalability of the schedulers, in terms of throughput, circuit complexity, and power consumption, based on implementation technology, considering the dramatic improvements expected in the availability of high-speed programmable logic and embedded processors on the same chip.

A Hierarchical Block-Floating-Point Arithmetic

In order to give an answer to a question of the arithmetic in future DSP architectures for mobile communication applications, the signal processing quality of different arithmetic representations has been studied. Based on the result, a new approach for implementing block-floating-point arithmetic is proposed. This approach intends to preserve the least-significant-bits (LSBs) to improve signal processing quality. The preservation of LSBs is automatically and perfectly done by hardware. Serveral simulation results show that the proposed block-floating-point implementation provides improved SNRs over conventional block-floating-point implementations. For the same number of bits in the memory for each representation, the SNRs better than floating-point are also observed. For multiple datapath DSPs, this implementation also requires significantly less hardware complexity than floating-point.

Optimal Interconnections in the Design of Microprocessors and Digital Systems

This paper recasts the multiple data path assignment problem solved by Torng and Wilhelm by the dynamic programming method [1] into a minimal covering problem following a switching theoretic approach. The concept of bus compatibility for the data transfers is used to obtain the various ways of interconnecting the circuit modules with the minimum number of buses that allow concurrent data transfers. These have been called the feasible solutions of the problem. The minimal cost solutions are obtained by assigning weights to the bus-compatible sets present in the feasible solutions. Minimization of the cost of the solution by increasing the number of buses is also discussed.

Optimal Interconnections in the Design of Microprocessors and Digital Systems

This paper recasts the multiple data path assignment problem solved by Torng and Wilhelm by the dynamic programming method [1] into a minimal covering problem following a switching theoretic approach. The concept of bus compatibility for the data transfers is used to obtain the various ways of interconnecting the circuit modules with the minimum number of buses that allow concurrent data transfers. These have been called the feasible solutions of the problem. The minimal cost solutions are obtained by assigning weights to the bus-compatible sets present in the feasible solutions. Minimization of the cost of the solution by increasing the number of buses is also discussed.

The IBM 3850 mass storage system: Design aspects

The IBM 3850 mass storage system is a new concept in large data base storage. This paper explores the principal design objectives and the options chosen in designing the hardware and the data flow for the system. The 3850 is an approach that provides up to 472 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> bytes of storage, gives reasonable on-line storage cost comparable to manually loaded flexible media products such as half-inch tape drives, provides internally controlled data staging at the request of the host processor, and provides a parallel-path data flow. The parallel-path data flow in turn provides multiple staging and destaging-plus increased availability of data--by using full multiple data paths for all data.